1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops -enable-subreg-liveness %s -o - --verify-machineinstrs | FileCheck %s 3 4--- | 5 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 6 target triple = "thumbv8.1m.main-arm-none-eabi" 7 8 define i32 @test(ptr nocapture readnone %x, ptr noalias %y, i32 %n, <4 x i32> %0, <4 x i32> %1, <4 x i32> %2, <4 x i32> %3, <4 x i32> %p) { 9 entry: 10 %cmp13 = icmp sgt i32 %n, 0 11 br i1 %cmp13, label %while.body.preheader, label %while.end 12 13 while.body.preheader: ; preds = %entry 14 %4 = add i32 %n, 3 15 %smin = call i32 @llvm.smin.i32(i32 %n, i32 4) 16 %5 = sub i32 %4, %smin 17 %6 = lshr i32 %5, 2 18 %7 = add nuw nsw i32 %6, 1 19 %8 = call i32 @llvm.start.loop.iterations.i32(i32 %7) 20 br label %while.body 21 22 while.body: ; preds = %while.body.preheader, %while.body 23 %y.addr.016 = phi ptr [ %add.ptr, %while.body ], [ %y, %while.body.preheader ] 24 %s.015 = phi <4 x i32> [ %mul, %while.body ], [ <i32 1, i32 1, i32 1, i32 1>, %while.body.preheader ] 25 %n.addr.014 = phi i32 [ %12, %while.body ], [ %n, %while.body.preheader ] 26 %9 = phi i32 [ %8, %while.body.preheader ], [ %13, %while.body ] 27 %y.addr.0161 = bitcast ptr %y.addr.016 to ptr 28 %10 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.014) 29 %11 = tail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %y.addr.0161, i32 4, <4 x i1> %10, <4 x i32> zeroinitializer) 30 %mul = mul <4 x i32> %11, %s.015 31 %add.ptr = getelementptr inbounds i32, ptr %y.addr.016, i32 4 32 %12 = add i32 %n.addr.014, -4 33 %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %9, i32 1) 34 %14 = icmp ne i32 %13, 0 35 br i1 %14, label %while.body, label %while.end 36 37 while.end: ; preds = %while.body, %entry 38 %s.0.lcssa = phi <4 x i32> [ <i32 1, i32 1, i32 1, i32 1>, %entry ], [ %mul, %while.body ] 39 %vecext = extractelement <4 x i32> %s.0.lcssa, i32 0 40 %vecext5 = extractelement <4 x i32> %s.0.lcssa, i32 1 41 %add = add nsw i32 %vecext, %vecext5 42 ret i32 %add 43 } 44 45 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1 46 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) #2 47 declare i32 @llvm.smin.i32(i32, i32) #3 48 declare i32 @llvm.start.loop.iterations.i32(i32) #4 49 declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #4 50 51... 52--- 53name: test 54tracksRegLiveness: true 55liveins: 56 - { reg: '$r1', virtual-reg: '' } 57 - { reg: '$r2', virtual-reg: '' } 58fixedStack: 59 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, 60 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 61 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 62stack: 63 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 64 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 65 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 66 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 67 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 68 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 69body: | 70 ; CHECK-LABEL: name: test 71 ; CHECK: bb.0.entry: 72 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.3(0x30000000) 73 ; CHECK-NEXT: liveins: $lr, $r1, $r2, $r7 74 ; CHECK-NEXT: {{ $}} 75 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 76 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 77 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 78 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 79 ; CHECK-NEXT: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 80 ; CHECK-NEXT: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr 81 ; CHECK-NEXT: {{ $}} 82 ; CHECK-NEXT: bb.1.while.body.preheader: 83 ; CHECK-NEXT: successors: %bb.2(0x80000000) 84 ; CHECK-NEXT: liveins: $r1, $r2 85 ; CHECK-NEXT: {{ $}} 86 ; CHECK-NEXT: $r0 = tMOVr $r2, 14 /* CC::al */, $noreg 87 ; CHECK-NEXT: tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr 88 ; CHECK-NEXT: t2IT 10, 8, implicit-def $itstate 89 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r0, implicit killed $itstate 90 ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBrr renamable $r2, killed renamable $r0, 14 /* CC::al */, $noreg 91 ; CHECK-NEXT: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 3, 14 /* CC::al */, $noreg 92 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 93 ; CHECK-NEXT: renamable $r0 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r0, 19, 14 /* CC::al */, $noreg, $noreg 94 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0 95 ; CHECK-NEXT: $lr = t2DLS killed renamable $r0 96 ; CHECK-NEXT: {{ $}} 97 ; CHECK-NEXT: bb.2.while.body (align 4): 98 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.4(0x04000000) 99 ; CHECK-NEXT: liveins: $lr, $q0, $r1, $r2 100 ; CHECK-NEXT: {{ $}} 101 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 102 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 103 ; CHECK-NEXT: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr, $lr :: (load (s128) from %ir.y.addr.0161, align 4) 104 ; CHECK-NEXT: renamable $q0 = MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $lr, undef renamable $q0 105 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 106 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 107 ; CHECK-NEXT: tB %bb.4, 14 /* CC::al */, $noreg 108 ; CHECK-NEXT: {{ $}} 109 ; CHECK-NEXT: bb.3: 110 ; CHECK-NEXT: successors: %bb.4(0x80000000) 111 ; CHECK-NEXT: {{ $}} 112 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0 113 ; CHECK-NEXT: {{ $}} 114 ; CHECK-NEXT: bb.4.while.end: 115 ; CHECK-NEXT: liveins: $d0 116 ; CHECK-NEXT: {{ $}} 117 ; CHECK-NEXT: renamable $r0, renamable $r1 = VMOVRRD killed renamable $d0, 14 /* CC::al */, $noreg 118 ; CHECK-NEXT: renamable $r0 = nsw tADDhirr killed renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg 119 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 120 bb.0.entry: 121 successors: %bb.1(0x50000000), %bb.3(0x30000000) 122 liveins: $r1, $r2, $r7, $lr 123 124 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 125 frame-setup CFI_INSTRUCTION def_cfa_offset 8 126 frame-setup CFI_INSTRUCTION offset $lr, -4 127 frame-setup CFI_INSTRUCTION offset $r7, -8 128 tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 129 tBcc %bb.3, 11 /* CC::lt */, killed $cpsr 130 131 bb.1.while.body.preheader: 132 successors: %bb.2(0x80000000) 133 liveins: $r1, $r2 134 135 $r0 = tMOVr $r2, 14 /* CC::al */, $noreg 136 tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr 137 t2IT 10, 8, implicit-def $itstate 138 renamable $r0 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r0, implicit killed $itstate 139 renamable $r0, dead $cpsr = tSUBrr renamable $r2, killed renamable $r0, 14 /* CC::al */, $noreg 140 renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 3, 14 /* CC::al */, $noreg 141 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 142 renamable $r0 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r0, 19, 14 /* CC::al */, $noreg, $noreg 143 renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0 144 renamable $lr = t2DoLoopStartTP killed renamable $r0, renamable $r2 145 146 bb.2.while.body (align 4): 147 successors: %bb.2(0x7c000000), %bb.4(0x04000000) 148 liveins: $lr, $q0:0x000000000000003C, $r1, $r2 149 150 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 151 MVE_VPST 8, implicit $vpr 152 renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr, $lr :: (load (s128) from %ir.y.addr.0161, align 4) 153 renamable $q0 = MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $lr, undef renamable $q0 154 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 155 renamable $lr = t2LoopEndDec killed renamable $lr, %bb.2, implicit-def dead $cpsr 156 tB %bb.4, 14 /* CC::al */, $noreg 157 158 bb.3: 159 successors: %bb.4(0x80000000) 160 161 renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0 162 163 bb.4.while.end: 164 liveins: $q0:0x000000000000000C 165 166 renamable $r0, renamable $r1 = VMOVRRD killed renamable $d0, 14 /* CC::al */, $noreg 167 renamable $r0 = nsw tADDhirr killed renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg 168 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 169 170... 171