1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=armv8.1m.main -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 source_filename = "size-limit.ll" 6 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 7 target triple = "thumbv8.1m.main" 8 9 define dso_local arm_aapcscc void @size_limit(ptr nocapture %a, ptr nocapture readonly %b, ptr nocapture readonly %c, i32 %N) { 10 entry: 11 %cmp8 = icmp eq i32 %N, 0 12 br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader 13 14 for.body.preheader: ; preds = %entry 15 %scevgep = getelementptr i32, ptr %a, i32 -1 16 %scevgep4 = getelementptr i32, ptr %c, i32 -1 17 %scevgep8 = getelementptr i32, ptr %b, i32 -1 18 %start = call i32 @llvm.start.loop.iterations.i32(i32 %N) 19 br label %for.body 20 21 for.cond.cleanup: ; preds = %for.body, %entry 22 ret void 23 24 for.body: ; preds = %for.body, %for.body.preheader 25 %lsr.iv9 = phi ptr [ %scevgep8, %for.body.preheader ], [ %scevgep10, %for.body ] 26 %lsr.iv5 = phi ptr [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ] 27 %lsr.iv1 = phi ptr [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ] 28 %0 = phi i32 [ %start, %for.body.preheader ], [ %3, %for.body ] 29 %size = call i32 @llvm.arm.space(i32 4070, i32 undef) 30 %scevgep3 = getelementptr i32, ptr %lsr.iv9, i32 1 31 %1 = load i32, ptr %scevgep3, align 4 32 %scevgep7 = getelementptr i32, ptr %lsr.iv5, i32 1 33 %2 = load i32, ptr %scevgep7, align 4 34 %mul = mul nsw i32 %2, %1 35 %scevgep11 = getelementptr i32, ptr %lsr.iv1, i32 1 36 store i32 %mul, ptr %scevgep11, align 4 37 %scevgep2 = getelementptr i32, ptr %lsr.iv1, i32 1 38 %scevgep6 = getelementptr i32, ptr %lsr.iv5, i32 1 39 %scevgep10 = getelementptr i32, ptr %lsr.iv9, i32 1 40 %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) 41 %4 = icmp ne i32 %3, 0 42 br i1 %4, label %for.body, label %for.cond.cleanup 43 } 44 45 declare i32 @llvm.arm.space(i32 immarg, i32) #0 46 47 declare i32 @llvm.start.loop.iterations.i32(i32) #1 48 49 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 50 51 declare void @llvm.stackprotector(ptr, ptr) #0 52 53 attributes #0 = { nounwind } 54 attributes #1 = { noduplicate nounwind } 55 56... 57--- 58name: size_limit 59alignment: 2 60exposesReturnsTwice: false 61legalized: false 62regBankSelected: false 63selected: false 64failedISel: false 65tracksRegLiveness: true 66hasWinCFI: false 67registers: [] 68liveins: 69 - { reg: '$r0', virtual-reg: '' } 70 - { reg: '$r1', virtual-reg: '' } 71 - { reg: '$r2', virtual-reg: '' } 72 - { reg: '$r3', virtual-reg: '' } 73frameInfo: 74 isFrameAddressTaken: false 75 isReturnAddressTaken: false 76 hasStackMap: false 77 hasPatchPoint: false 78 stackSize: 8 79 offsetAdjustment: 0 80 maxAlignment: 4 81 adjustsStack: false 82 hasCalls: false 83 stackProtector: '' 84 maxCallFrameSize: 0 85 cvBytesOfCalleeSavedRegisters: 0 86 hasOpaqueSPAdjustment: false 87 hasVAStart: false 88 hasMustTailInVarArgFunc: false 89 localFrameSize: 0 90 savePoint: '' 91 restorePoint: '' 92fixedStack: [] 93stack: 94 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 95 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 96 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 97 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 98 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 99 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 100callSites: [] 101constants: [] 102machineFunctionInfo: {} 103body: | 104 ; CHECK-LABEL: name: size_limit 105 ; CHECK: bb.0.entry: 106 ; CHECK-NEXT: successors: %bb.1(0x80000000) 107 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 108 ; CHECK-NEXT: {{ $}} 109 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 110 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 111 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 112 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 113 ; CHECK-NEXT: tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 114 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 115 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 116 ; CHECK-NEXT: {{ $}} 117 ; CHECK-NEXT: bb.1.for.body.preheader: 118 ; CHECK-NEXT: successors: %bb.2(0x80000000) 119 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 120 ; CHECK-NEXT: {{ $}} 121 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 122 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 123 ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg 124 ; CHECK-NEXT: dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg 125 ; CHECK-NEXT: $lr = t2DLS killed $r3 126 ; CHECK-NEXT: {{ $}} 127 ; CHECK-NEXT: bb.2.for.body: 128 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 129 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 130 ; CHECK-NEXT: {{ $}} 131 ; CHECK-NEXT: dead renamable $r3 = SPACE 4070, undef renamable $r0 132 ; CHECK-NEXT: renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) 133 ; CHECK-NEXT: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) 134 ; CHECK-NEXT: renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14 /* CC::al */, $noreg 135 ; CHECK-NEXT: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep11) 136 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 137 ; CHECK-NEXT: {{ $}} 138 ; CHECK-NEXT: bb.3.for.cond.cleanup: 139 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 140 bb.0.entry: 141 successors: %bb.1(0x80000000) 142 liveins: $r0, $r1, $r2, $r3, $r7, $lr 143 144 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 145 frame-setup CFI_INSTRUCTION def_cfa_offset 8 146 frame-setup CFI_INSTRUCTION offset $lr, -4 147 frame-setup CFI_INSTRUCTION offset $r7, -8 148 tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr 149 t2IT 0, 8, implicit-def $itstate 150 tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate 151 152 bb.1.for.body.preheader: 153 successors: %bb.2(0x80000000) 154 liveins: $r0, $r1, $r2, $r3, $r7, $lr 155 156 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg 157 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 158 renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg 159 $lr = tMOVr $r3, 14, $noreg 160 $lr = t2DoLoopStart killed $r3 161 162 bb.2.for.body: 163 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 164 liveins: $lr, $r0, $r1, $r2 165 166 dead renamable $r3 = SPACE 4070, undef renamable $r0 167 renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load (s32) from %ir.scevgep3) 168 renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load (s32) from %ir.scevgep7) 169 renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14, $noreg 170 early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store (s32) into %ir.scevgep11) 171 renamable $lr = t2LoopDec killed renamable $lr, 1 172 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 173 tB %bb.3, 14, $noreg 174 175 bb.3.for.cond.cleanup: 176 tPOP_RET 14, $noreg, def $r7, def $pc 177 178... 179