1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s 3 4# TODO: Explore the preheader to remove the redundant tMOVr 5 6--- | 7 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 8 target triple = "thumbv8.1m.main" 9 10 define i32 @do_copy(i32 %n, ptr nocapture %p, ptr nocapture readonly %q) { 11 entry: 12 %scevgep = getelementptr i32, ptr %q, i32 -1 13 %scevgep3 = getelementptr i32, ptr %p, i32 -1 14 %start = call i32 @llvm.start.loop.iterations.i32(i32 %n) 15 br label %preheader 16 17 preheader: 18 br label %while.body 19 20 while.body: ; preds = %while.body, %entry 21 %lsr.iv4 = phi ptr [ %scevgep5, %while.body ], [ %scevgep3, %preheader ] 22 %lsr.iv = phi ptr [ %scevgep1, %while.body ], [ %scevgep, %preheader ] 23 %0 = phi i32 [ %start, %preheader ], [ %2, %while.body ] 24 %scevgep6 = getelementptr i32, ptr %lsr.iv, i32 1 25 %scevgep2 = getelementptr i32, ptr %lsr.iv4, i32 1 26 %1 = load i32, ptr %scevgep6, align 4 27 store i32 %1, ptr %scevgep2, align 4 28 %scevgep1 = getelementptr i32, ptr %lsr.iv, i32 1 29 %scevgep5 = getelementptr i32, ptr %lsr.iv4, i32 1 30 %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) 31 %3 = icmp ne i32 %2, 0 32 br i1 %3, label %while.body, label %while.end 33 34 while.end: ; preds = %while.body 35 ret i32 0 36 } 37 38 declare i32 @llvm.start.loop.iterations.i32(i32) #0 39 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 40 41 attributes #0 = { noduplicate nounwind } 42 attributes #1 = { nounwind } 43 44... 45--- 46name: do_copy 47alignment: 2 48exposesReturnsTwice: false 49legalized: false 50regBankSelected: false 51selected: false 52failedISel: false 53tracksRegLiveness: true 54hasWinCFI: false 55registers: [] 56liveins: 57 - { reg: '$r0', virtual-reg: '' } 58 - { reg: '$r1', virtual-reg: '' } 59 - { reg: '$r2', virtual-reg: '' } 60frameInfo: 61 isFrameAddressTaken: false 62 isReturnAddressTaken: false 63 hasStackMap: false 64 hasPatchPoint: false 65 stackSize: 8 66 offsetAdjustment: 0 67 maxAlignment: 4 68 adjustsStack: false 69 hasCalls: false 70 stackProtector: '' 71 maxCallFrameSize: 0 72 cvBytesOfCalleeSavedRegisters: 0 73 hasOpaqueSPAdjustment: false 74 hasVAStart: false 75 hasMustTailInVarArgFunc: false 76 localFrameSize: 0 77 savePoint: '' 78 restorePoint: '' 79fixedStack: [] 80stack: 81 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 82 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 83 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 84 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 85 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 86 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 87callSites: [] 88constants: [] 89machineFunctionInfo: {} 90body: | 91 ; CHECK-LABEL: name: do_copy 92 ; CHECK: bb.0.entry: 93 ; CHECK-NEXT: successors: %bb.1(0x80000000) 94 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 95 ; CHECK-NEXT: {{ $}} 96 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 97 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 98 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 99 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 100 ; CHECK-NEXT: dead $lr = t2DLS killed $r0 101 ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 /* CC::al */, $noreg 102 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg 103 ; CHECK-NEXT: {{ $}} 104 ; CHECK-NEXT: bb.1.preheader: 105 ; CHECK-NEXT: successors: %bb.2(0x80000000) 106 ; CHECK-NEXT: liveins: $r0, $r1 107 ; CHECK-NEXT: {{ $}} 108 ; CHECK-NEXT: $lr = tMOVr $r0, 14 /* CC::al */, $noreg 109 ; CHECK-NEXT: {{ $}} 110 ; CHECK-NEXT: bb.2.while.body: 111 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 112 ; CHECK-NEXT: liveins: $lr, $r0, $r1 113 ; CHECK-NEXT: {{ $}} 114 ; CHECK-NEXT: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep6) 115 ; CHECK-NEXT: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep2) 116 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 117 ; CHECK-NEXT: {{ $}} 118 ; CHECK-NEXT: bb.3.while.end: 119 ; CHECK-NEXT: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 120 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 121 bb.0.entry: 122 successors: %bb.1(0x80000000) 123 liveins: $r0, $r1, $r2, $r7, $lr 124 125 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 126 frame-setup CFI_INSTRUCTION def_cfa_offset 8 127 frame-setup CFI_INSTRUCTION offset $lr, -4 128 frame-setup CFI_INSTRUCTION offset $r7, -8 129 $lr = t2DoLoopStart $r0 130 renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg 131 renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg 132 133 bb.1.preheader: 134 successors: %bb.2(0x80000000) 135 liveins: $r0, $r1 136 $lr = tMOVr $r0, 14, $noreg 137 138 bb.2.while.body: 139 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 140 liveins: $lr, $r0, $r1 141 142 renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load (s32) from %ir.scevgep6) 143 early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store (s32) into %ir.scevgep2) 144 renamable $lr = t2LoopDec killed renamable $lr, 1 145 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 146 tB %bb.3, 14, $noreg 147 148 bb.3.while.end: 149 $r0, dead $cpsr = tMOVi8 0, 14, $noreg 150 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 151 152... 153