1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 6 target triple = "thumbv8.1m.main" 7 8 define void @ne_trip_count(i1 zeroext %t1, ptr nocapture %a, ptr nocapture readonly %b, i32 %N) #0 { 9 entry: 10 %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N) 11 br i1 %0, label %do.body.preheader, label %if.end 12 13 do.body.preheader: ; preds = %entry 14 %scevgep2 = getelementptr i32, ptr %a, i32 -1 15 %scevgep5 = getelementptr i32, ptr %b, i32 -1 16 br label %do.body 17 18 do.body: ; preds = %do.body, %do.body.preheader 19 %lsr.iv6 = phi ptr [ %scevgep5, %do.body.preheader ], [ %scevgep7, %do.body ] 20 %lsr.iv = phi ptr [ %scevgep2, %do.body.preheader ], [ %scevgep3, %do.body ] 21 %1 = phi i32 [ %2, %do.body ], [ %N, %do.body.preheader ] 22 %scevgep = getelementptr i32, ptr %lsr.iv6, i32 1 23 %scevgep1 = getelementptr i32, ptr %lsr.iv, i32 1 24 %size = call i32 @llvm.arm.space(i32 4096, i32 undef) 25 %tmp = load i32, ptr %scevgep, align 4 26 store i32 %tmp, ptr %scevgep1, align 4 27 %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1) 28 %3 = icmp ne i32 %2, 0 29 %scevgep3 = getelementptr i32, ptr %lsr.iv, i32 1 30 %scevgep7 = getelementptr i32, ptr %lsr.iv6, i32 1 31 br i1 %3, label %do.body, label %if.end 32 33 if.end: ; preds = %do.body, %entry 34 ret void 35 } 36 37 declare i32 @llvm.arm.space(i32 immarg, i32) #1 38 39 declare i1 @llvm.test.set.loop.iterations.i32(i32) #2 40 41 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2 42 43 attributes #0 = { "target-features"="+lob" } 44 attributes #1 = { nounwind } 45 attributes #2 = { noduplicate nounwind } 46 47... 48--- 49name: ne_trip_count 50alignment: 2 51exposesReturnsTwice: false 52legalized: false 53regBankSelected: false 54selected: false 55failedISel: false 56tracksRegLiveness: true 57hasWinCFI: false 58registers: [] 59liveins: 60 - { reg: '$r1', virtual-reg: '' } 61 - { reg: '$r2', virtual-reg: '' } 62 - { reg: '$r3', virtual-reg: '' } 63frameInfo: 64 isFrameAddressTaken: false 65 isReturnAddressTaken: false 66 hasStackMap: false 67 hasPatchPoint: false 68 stackSize: 8 69 offsetAdjustment: 0 70 maxAlignment: 4 71 adjustsStack: false 72 hasCalls: false 73 stackProtector: '' 74 maxCallFrameSize: 0 75 cvBytesOfCalleeSavedRegisters: 0 76 hasOpaqueSPAdjustment: false 77 hasVAStart: false 78 hasMustTailInVarArgFunc: false 79 localFrameSize: 0 80 savePoint: '' 81 restorePoint: '' 82fixedStack: [] 83stack: 84 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 85 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 86 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 87 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 88 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 89 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 90callSites: [] 91constants: [] 92machineFunctionInfo: {} 93body: | 94 ; CHECK-LABEL: name: ne_trip_count 95 ; CHECK: bb.0.entry: 96 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000) 97 ; CHECK-NEXT: liveins: $lr, $r1, $r2, $r3, $r7 98 ; CHECK-NEXT: {{ $}} 99 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 100 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 101 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 102 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 103 ; CHECK-NEXT: dead $lr = t2SUBri $r3, 0, 14 /* CC::al */, $noreg, def $cpsr 104 ; CHECK-NEXT: t2Bcc %bb.3, 0 /* CC::eq */, killed $cpsr 105 ; CHECK-NEXT: tB %bb.1, 14 /* CC::al */, $noreg 106 ; CHECK-NEXT: {{ $}} 107 ; CHECK-NEXT: bb.1.do.body.preheader: 108 ; CHECK-NEXT: successors: %bb.2(0x80000000) 109 ; CHECK-NEXT: liveins: $r1, $r2, $r3 110 ; CHECK-NEXT: {{ $}} 111 ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg 112 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 113 ; CHECK-NEXT: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg 114 ; CHECK-NEXT: {{ $}} 115 ; CHECK-NEXT: bb.2.do.body: 116 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 117 ; CHECK-NEXT: liveins: $lr, $r0, $r1 118 ; CHECK-NEXT: {{ $}} 119 ; CHECK-NEXT: dead renamable $r2 = SPACE 4096, undef renamable $r0 120 ; CHECK-NEXT: renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep) 121 ; CHECK-NEXT: early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep1) 122 ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr 123 ; CHECK-NEXT: t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr 124 ; CHECK-NEXT: tB %bb.3, 14 /* CC::al */, $noreg 125 ; CHECK-NEXT: {{ $}} 126 ; CHECK-NEXT: bb.3.if.end: 127 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 128 bb.0.entry: 129 successors: %bb.1(0x40000000), %bb.3(0x40000000) 130 liveins: $r1, $r2, $r3, $r7, $lr 131 132 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 133 frame-setup CFI_INSTRUCTION def_cfa_offset 8 134 frame-setup CFI_INSTRUCTION offset $lr, -4 135 frame-setup CFI_INSTRUCTION offset $r7, -8 136 $lr = t2WhileLoopStartLR $r3, %bb.3, implicit-def dead $cpsr 137 tB %bb.1, 14, $noreg 138 139 bb.1.do.body.preheader: 140 successors: %bb.2(0x80000000) 141 liveins: $r1, $r2, $r3 142 143 renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg 144 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg 145 $lr = tMOVr killed $r3, 14, $noreg 146 147 bb.2.do.body: 148 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 149 liveins: $lr, $r0, $r1 150 151 dead renamable $r2 = SPACE 4096, undef renamable $r0 152 renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load (s32) from %ir.scevgep) 153 early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14, $noreg :: (store (s32) into %ir.scevgep1) 154 renamable $lr = t2LoopDec killed renamable $lr, 1 155 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 156 tB %bb.3, 14, $noreg 157 158 bb.3.if.end: 159 tPOP_RET 14, $noreg, def $r7, def $pc 160 161... 162