xref: /llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir (revision 59c6bd156cc8b42758ce90909615748e21c6eee2) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
3
4--- |
5  define dso_local arm_aapcs_vfpcc void @remove_mov_lr_chain(ptr nocapture readonly %pSrc, ptr nocapture %pDst, i32 %blockSize) #0 {
6  entry:
7    %cmp5 = icmp eq i32 %blockSize, 0
8    br i1 %cmp5, label %while.end, label %while.body.preheader
9
10  while.body.preheader:                             ; preds = %entry
11    %min.iters.check = icmp ult i32 %blockSize, 4
12    br i1 %min.iters.check, label %while.body.preheader19, label %vector.memcheck
13
14  vector.memcheck:                                  ; preds = %while.body.preheader
15    %scevgep = getelementptr float, ptr %pDst, i32 %blockSize
16    %scevgep12 = getelementptr float, ptr %pSrc, i32 %blockSize
17    %bound0 = icmp ugt ptr %scevgep12, %pDst
18    %bound1 = icmp ugt ptr %scevgep, %pSrc
19    %found.conflict = and i1 %bound0, %bound1
20    %0 = lshr i32 %blockSize, 2
21    %1 = shl nuw i32 %0, 2
22    %2 = add i32 %1, -4
23    %3 = lshr i32 %2, 2
24    %4 = add nuw nsw i32 %3, 1
25    br i1 %found.conflict, label %while.body.preheader19, label %vector.ph
26
27  vector.ph:                                        ; preds = %vector.memcheck
28    %n.vec = and i32 %blockSize, -4
29    %ind.end = sub i32 %blockSize, %n.vec
30    %ind.end15 = getelementptr float, ptr %pSrc, i32 %n.vec
31    %ind.end17 = getelementptr float, ptr %pDst, i32 %n.vec
32    %scevgep9 = getelementptr float, ptr %pDst, i32 -4
33    %scevgep14 = getelementptr float, ptr %pSrc, i32 -4
34    %start1 = call i32 @llvm.start.loop.iterations.i32(i32 %4)
35    br label %vector.body
36
37  vector.body:                                      ; preds = %vector.body, %vector.ph
38    %lsr.iv15 = phi ptr [ %scevgep16, %vector.body ], [ %scevgep14, %vector.ph ]
39    %lsr.iv10 = phi ptr [ %scevgep11, %vector.body ], [ %scevgep9, %vector.ph ]
40    %5 = phi i32 [ %start1, %vector.ph ], [ %7, %vector.body ]
41    %scevgep18 = getelementptr <4 x float>, ptr %lsr.iv15, i32 1
42    %wide.load = load <4 x float>, ptr %scevgep18, align 4
43    %6 = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %wide.load)
44    %scevgep13 = getelementptr <4 x float>, ptr %lsr.iv10, i32 1
45    store <4 x float> %6, ptr %scevgep13, align 4
46    %scevgep11 = getelementptr float, ptr %lsr.iv10, i32 4
47    %scevgep16 = getelementptr float, ptr %lsr.iv15, i32 4
48    %7 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)
49    %8 = icmp ne i32 %7, 0
50    br i1 %8, label %vector.body, label %middle.block
51
52  middle.block:                                     ; preds = %vector.body
53    %cmp.n = icmp eq i32 %n.vec, %blockSize
54    br i1 %cmp.n, label %while.end, label %while.body.preheader19
55
56  while.body.preheader19:                           ; preds = %middle.block, %vector.memcheck, %while.body.preheader
57    %blkCnt.08.ph = phi i32 [ %blockSize, %vector.memcheck ], [ %blockSize, %while.body.preheader ], [ %ind.end, %middle.block ]
58    %pSrc.addr.07.ph = phi ptr [ %pSrc, %vector.memcheck ], [ %pSrc, %while.body.preheader ], [ %ind.end15, %middle.block ]
59    %pDst.addr.06.ph = phi ptr [ %pDst, %vector.memcheck ], [ %pDst, %while.body.preheader ], [ %ind.end17, %middle.block ]
60    %scevgep1 = getelementptr float, ptr %pSrc.addr.07.ph, i32 -1
61    %scevgep4 = getelementptr float, ptr %pDst.addr.06.ph, i32 -1
62    %start2 = call i32 @llvm.start.loop.iterations.i32(i32 %blkCnt.08.ph)
63    br label %while.body
64
65  while.body:                                       ; preds = %while.body, %while.body.preheader19
66    %lsr.iv5 = phi ptr [ %scevgep6, %while.body ], [ %scevgep4, %while.body.preheader19 ]
67    %lsr.iv = phi ptr [ %scevgep2, %while.body ], [ %scevgep1, %while.body.preheader19 ]
68    %9 = phi i32 [ %start2, %while.body.preheader19 ], [ %12, %while.body ]
69    %scevgep3 = getelementptr float, ptr %lsr.iv, i32 1
70    %scevgep7 = getelementptr float, ptr %lsr.iv5, i32 1
71    %10 = load float, ptr %scevgep3, align 4
72    %11 = tail call fast float @llvm.fabs.f32(float %10)
73    store float %11, ptr %scevgep7, align 4
74    %scevgep2 = getelementptr float, ptr %lsr.iv, i32 1
75    %scevgep6 = getelementptr float, ptr %lsr.iv5, i32 1
76    %12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %9, i32 1)
77    %13 = icmp ne i32 %12, 0
78    br i1 %13, label %while.body, label %while.end
79
80  while.end:                                        ; preds = %while.body, %middle.block, %entry
81    ret void
82  }
83  declare float @llvm.fabs.f32(float)
84  declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
85  declare i32 @llvm.start.loop.iterations.i32(i32)
86  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
87
88...
89---
90name:            remove_mov_lr_chain
91alignment:       2
92exposesReturnsTwice: false
93legalized:       false
94regBankSelected: false
95selected:        false
96failedISel:      false
97tracksRegLiveness: true
98hasWinCFI:       false
99registers:       []
100liveins:
101  - { reg: '$r0', virtual-reg: '' }
102  - { reg: '$r1', virtual-reg: '' }
103  - { reg: '$r2', virtual-reg: '' }
104frameInfo:
105  isFrameAddressTaken: false
106  isReturnAddressTaken: false
107  hasStackMap:     false
108  hasPatchPoint:   false
109  stackSize:       16
110  offsetAdjustment: 0
111  maxAlignment:    4
112  adjustsStack:    false
113  hasCalls:        false
114  stackProtector:  ''
115  maxCallFrameSize: 0
116  cvBytesOfCalleeSavedRegisters: 0
117  hasOpaqueSPAdjustment: false
118  hasVAStart:      false
119  hasMustTailInVarArgFunc: false
120  localFrameSize:  0
121  savePoint:       ''
122  restorePoint:    ''
123fixedStack:      []
124stack:
125  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
126      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
127      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
128  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
129      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
130      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
131  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
132      stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
133      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
134  - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
135      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
136      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
137callSites:       []
138constants:       []
139machineFunctionInfo: {}
140body:             |
141  ; CHECK-LABEL: name: remove_mov_lr_chain
142  ; CHECK: bb.0.entry:
143  ; CHECK-NEXT:   successors: %bb.9(0x30000000), %bb.1(0x50000000)
144  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r7
145  ; CHECK-NEXT: {{  $}}
146  ; CHECK-NEXT:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
147  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 16
148  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -4
149  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r7, -8
150  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r5, -12
151  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r4, -16
152  ; CHECK-NEXT:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
153  ; CHECK-NEXT:   tBcc %bb.9, 0 /* CC::eq */, killed $cpsr
154  ; CHECK-NEXT: {{  $}}
155  ; CHECK-NEXT: bb.1.while.body.preheader:
156  ; CHECK-NEXT:   successors: %bb.6(0x40000000), %bb.2(0x40000000)
157  ; CHECK-NEXT:   liveins: $r0, $r1, $r2
158  ; CHECK-NEXT: {{  $}}
159  ; CHECK-NEXT:   tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
160  ; CHECK-NEXT:   tBcc %bb.6, 3 /* CC::lo */, killed $cpsr
161  ; CHECK-NEXT: {{  $}}
162  ; CHECK-NEXT: bb.2.vector.memcheck:
163  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.6(0x40000000)
164  ; CHECK-NEXT:   liveins: $r0, $r1, $r2
165  ; CHECK-NEXT: {{  $}}
166  ; CHECK-NEXT:   renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14 /* CC::al */, $noreg, $noreg
167  ; CHECK-NEXT:   tCMPr killed renamable $r3, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
168  ; CHECK-NEXT:   t2IT 8, 4, implicit-def $itstate
169  ; CHECK-NEXT:   renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate
170  ; CHECK-NEXT:   tCMPr killed renamable $r3, renamable $r0, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
171  ; CHECK-NEXT:   tBcc %bb.6, 8 /* CC::hi */, killed $cpsr
172  ; CHECK-NEXT: {{  $}}
173  ; CHECK-NEXT: bb.3.vector.ph:
174  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
175  ; CHECK-NEXT:   liveins: $r0, $r1, $r2
176  ; CHECK-NEXT: {{  $}}
177  ; CHECK-NEXT:   renamable $r4 = t2BICri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg
178  ; CHECK-NEXT:   renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
179  ; CHECK-NEXT:   renamable $r12 = t2SUBri renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg
180  ; CHECK-NEXT:   renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14 /* CC::al */, $noreg
181  ; CHECK-NEXT:   renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
182  ; CHECK-NEXT:   renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
183  ; CHECK-NEXT:   dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg
184  ; CHECK-NEXT:   renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
185  ; CHECK-NEXT:   $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg
186  ; CHECK-NEXT:   renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
187  ; CHECK-NEXT:   renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
188  ; CHECK-NEXT: {{  $}}
189  ; CHECK-NEXT: bb.4.vector.body:
190  ; CHECK-NEXT:   successors: %bb.4(0x7c000000), %bb.5(0x04000000)
191  ; CHECK-NEXT:   liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12
192  ; CHECK-NEXT: {{  $}}
193  ; CHECK-NEXT:   renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep18, align 4)
194  ; CHECK-NEXT:   $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg
195  ; CHECK-NEXT:   renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
196  ; CHECK-NEXT:   renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg, $noreg :: (store (s128) into %ir.scevgep13, align 4)
197  ; CHECK-NEXT:   renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
198  ; CHECK-NEXT:   $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg
199  ; CHECK-NEXT:   tBcc %bb.4, 1 /* CC::ne */, killed $cpsr
200  ; CHECK-NEXT:   tB %bb.5, 14 /* CC::al */, $noreg
201  ; CHECK-NEXT: {{  $}}
202  ; CHECK-NEXT: bb.5.middle.block:
203  ; CHECK-NEXT:   successors: %bb.7(0x80000000)
204  ; CHECK-NEXT:   liveins: $r2, $r3, $r4, $r7, $r12
205  ; CHECK-NEXT: {{  $}}
206  ; CHECK-NEXT:   tCMPr killed renamable $r4, killed renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
207  ; CHECK-NEXT:   $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg
208  ; CHECK-NEXT:   t2IT 0, 8, implicit-def $itstate
209  ; CHECK-NEXT:   tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate
210  ; CHECK-NEXT:   tB %bb.7, 14 /* CC::al */, $noreg
211  ; CHECK-NEXT: {{  $}}
212  ; CHECK-NEXT: bb.6:
213  ; CHECK-NEXT:   successors: %bb.7(0x80000000)
214  ; CHECK-NEXT:   liveins: $r0, $r1, $r2
215  ; CHECK-NEXT: {{  $}}
216  ; CHECK-NEXT:   $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg
217  ; CHECK-NEXT:   $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg
218  ; CHECK-NEXT:   $r3 = tMOVr killed $r1, 14 /* CC::al */, $noreg
219  ; CHECK-NEXT: {{  $}}
220  ; CHECK-NEXT: bb.7.while.body.preheader19:
221  ; CHECK-NEXT:   successors: %bb.8(0x80000000)
222  ; CHECK-NEXT:   liveins: $lr, $r3, $r12
223  ; CHECK-NEXT: {{  $}}
224  ; CHECK-NEXT:   renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg
225  ; CHECK-NEXT:   renamable $r1 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
226  ; CHECK-NEXT: {{  $}}
227  ; CHECK-NEXT: bb.8.while.body:
228  ; CHECK-NEXT:   successors: %bb.8(0x7c000000), %bb.9(0x04000000)
229  ; CHECK-NEXT:   liveins: $lr, $r0, $r1
230  ; CHECK-NEXT: {{  $}}
231  ; CHECK-NEXT:   renamable $s0 = VLDRS renamable $r1, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3)
232  ; CHECK-NEXT:   renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
233  ; CHECK-NEXT:   renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14 /* CC::al */, $noreg
234  ; CHECK-NEXT:   VSTRS killed renamable $s0, renamable $r0, 1, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep7)
235  ; CHECK-NEXT:   renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
236  ; CHECK-NEXT:   $lr = t2LEUpdate killed renamable $lr, %bb.8
237  ; CHECK-NEXT: {{  $}}
238  ; CHECK-NEXT: bb.9.while.end:
239  ; CHECK-NEXT:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
240  bb.0.entry:
241    successors: %bb.9(0x30000000), %bb.1(0x50000000)
242    liveins: $r0, $r1, $r2, $r4, $r5, $r7, $lr
243
244    frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
245    frame-setup CFI_INSTRUCTION def_cfa_offset 16
246    frame-setup CFI_INSTRUCTION offset $lr, -4
247    frame-setup CFI_INSTRUCTION offset $r7, -8
248    frame-setup CFI_INSTRUCTION offset $r5, -12
249    frame-setup CFI_INSTRUCTION offset $r4, -16
250    tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
251    tBcc %bb.9, 0, killed $cpsr
252
253  bb.1.while.body.preheader:
254    successors: %bb.6(0x40000000), %bb.2(0x40000000)
255    liveins: $r0, $r1, $r2
256
257    tCMPi8 renamable $r2, 4, 14, $noreg, implicit-def $cpsr
258    tBcc %bb.6, 3, killed $cpsr
259
260  bb.2.vector.memcheck:
261    successors: %bb.3(0x40000000), %bb.6(0x40000000)
262    liveins: $r0, $r1, $r2
263
264    renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14, $noreg, $noreg
265    tCMPr killed renamable $r3, renamable $r1, 14, $noreg, implicit-def $cpsr
266    t2IT 8, 4, implicit-def $itstate
267    renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8, $cpsr, $noreg, implicit $itstate
268    tCMPr killed renamable $r3, renamable $r0, 8, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
269    tBcc %bb.6, 8, killed $cpsr
270
271  bb.3.vector.ph:
272    successors: %bb.4(0x80000000)
273    liveins: $r0, $r1, $r2
274
275    renamable $r4 = t2BICri renamable $r2, 3, 14, $noreg, $noreg
276    renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
277    renamable $r12 = t2SUBri renamable $r4, 4, 14, $noreg, $noreg
278    renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14, $noreg
279    renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
280    renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14, $noreg, $noreg
281    $lr = t2DoLoopStart renamable $r3
282    renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14, $noreg
283    $r5 = tMOVr killed $r3, 14, $noreg
284    renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14, $noreg, $noreg
285    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14, $noreg
286
287  bb.4.vector.body:
288    successors: %bb.4(0x7c000000), %bb.5(0x04000000)
289    liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12
290
291    renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep18, align 4)
292    $lr = tMOVr killed $r5, 14, $noreg
293    renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
294    renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg, $noreg :: (store (s128) into %ir.scevgep13, align 4)
295    renamable $lr = t2LoopDec killed renamable $lr, 1
296    $r5 = tMOVr $lr, 14, $noreg
297    t2LoopEnd killed renamable $lr, %bb.4, implicit-def dead $cpsr
298    tB %bb.5, 14, $noreg
299
300  bb.5.middle.block:
301    successors: %bb.7(0x80000000)
302    liveins: $r2, $r3, $r4, $r7, $r12
303
304    tCMPr killed renamable $r4, killed renamable $r2, 14, $noreg, implicit-def $cpsr
305    $lr = tMOVr killed $r7, 14, $noreg
306    t2IT 0, 8, implicit-def $itstate
307    tPOP_RET 0, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate
308    tB %bb.7, 14, $noreg
309
310  bb.6:
311    successors: %bb.7(0x80000000)
312    liveins: $r0, $r1, $r2
313
314    $lr = tMOVr killed $r2, 14, $noreg
315    $r12 = tMOVr killed $r0, 14, $noreg
316    $r3 = tMOVr killed $r1, 14, $noreg
317
318  bb.7.while.body.preheader19:
319    successors: %bb.8(0x80000000)
320    liveins: $lr, $r3, $r12
321
322    renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14, $noreg
323    renamable $r1 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
324    $lr = t2DoLoopStart renamable $lr
325
326  bb.8.while.body:
327    successors: %bb.8(0x7c000000), %bb.9(0x04000000)
328    liveins: $lr, $r0, $r1
329
330    renamable $s0 = VLDRS renamable $r1, 1, 14, $noreg :: (load (s32) from %ir.scevgep3)
331    renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg
332    renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14, $noreg
333    VSTRS killed renamable $s0, renamable $r0, 1, 14, $noreg :: (store (s32) into %ir.scevgep7)
334    renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg
335    renamable $lr = t2LoopDec killed renamable $lr, 1
336    t2LoopEnd renamable $lr, %bb.8, implicit-def dead $cpsr
337    tB %bb.9, 14, $noreg
338
339  bb.9.while.end:
340    tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc
341
342...
343