xref: /llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir (revision 59c6bd156cc8b42758ce90909615748e21c6eee2) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
3
4--- |
5  define dso_local arm_aapcs_vfpcc i32 @mul_var_i8(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) {
6  entry:
7    %cmp9.not = icmp eq i32 %N, 0
8    %0 = add i32 %N, 3
9    %1 = lshr i32 %0, 2
10    %2 = shl nuw i32 %1, 2
11    %3 = add i32 %2, -4
12    %4 = lshr i32 %3, 2
13    %5 = add nuw nsw i32 %4, 1
14    br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph
15
16  vector.ph:                                        ; preds = %entry
17    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
18    br label %vector.body
19
20  vector.body:                                      ; preds = %vector.body, %vector.ph
21    %lsr.iv14 = phi ptr [ %scevgep15, %vector.body ], [ %b, %vector.ph ]
22    %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]
23    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]
24    %6 = phi i32 [ %start, %vector.ph ], [ %15, %vector.body ]
25    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
26    %lsr.iv13 = bitcast ptr %lsr.iv to ptr
27    %lsr.iv1416 = bitcast ptr %lsr.iv14 to ptr
28    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
29    %9 = sub i32 %7, 4
30    %wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %lsr.iv13, i32 1, <4 x i1> %8, <4 x i8> undef)
31    %10 = zext <4 x i8> %wide.masked.load to <4 x i32>
32    %wide.masked.load12 = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %lsr.iv1416, i32 1, <4 x i1> %8, <4 x i8> undef)
33    %11 = zext <4 x i8> %wide.masked.load12 to <4 x i32>
34    %12 = mul nuw nsw <4 x i32> %11, %10
35    %13 = select <4 x i1> %8, <4 x i32> %12, <4 x i32> zeroinitializer
36    %14 = add <4 x i32> %vec.phi, %13
37    %scevgep = getelementptr i8, ptr %lsr.iv, i32 4
38    %scevgep15 = getelementptr i8, ptr %lsr.iv14, i32 4
39    %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
40    %16 = icmp ne i32 %15, 0
41    br i1 %16, label %vector.body, label %middle.block
42
43  middle.block:                                     ; preds = %vector.body
44    %17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)
45    br label %for.cond.cleanup
46
47  for.cond.cleanup:                                 ; preds = %middle.block, %entry
48    %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]
49    ret i32 %res.0.lcssa
50  }
51
52  define dso_local arm_aapcs_vfpcc i32 @add_var_i8(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) {
53  entry:
54    %cmp10.not = icmp eq i32 %N, 0
55    %0 = add i32 %N, 3
56    %1 = lshr i32 %0, 2
57    %2 = shl nuw i32 %1, 2
58    %3 = add i32 %2, -4
59    %4 = lshr i32 %3, 2
60    %5 = add nuw nsw i32 %4, 1
61    br i1 %cmp10.not, label %for.cond.cleanup, label %vector.ph
62
63  vector.ph:                                        ; preds = %entry
64    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
65    br label %vector.body
66
67  vector.body:                                      ; preds = %vector.body, %vector.ph
68    %lsr.iv15 = phi ptr [ %scevgep16, %vector.body ], [ %b, %vector.ph ]
69    %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]
70    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]
71    %6 = phi i32 [ %start, %vector.ph ], [ %15, %vector.body ]
72    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
73    %lsr.iv14 = bitcast ptr %lsr.iv to ptr
74    %lsr.iv1517 = bitcast ptr %lsr.iv15 to ptr
75    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
76    %9 = sub i32 %7, 4
77    %wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %lsr.iv14, i32 1, <4 x i1> %8, <4 x i8> undef)
78    %10 = zext <4 x i8> %wide.masked.load to <4 x i32>
79    %wide.masked.load13 = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %lsr.iv1517, i32 1, <4 x i1> %8, <4 x i8> undef)
80    %11 = zext <4 x i8> %wide.masked.load13 to <4 x i32>
81    %12 = add <4 x i32> %vec.phi, %10
82    %13 = add <4 x i32> %12, %11
83    %14 = select <4 x i1> %8, <4 x i32> %13, <4 x i32> %vec.phi
84    %scevgep = getelementptr i8, ptr %lsr.iv, i32 4
85    %scevgep16 = getelementptr i8, ptr %lsr.iv15, i32 4
86    %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
87    %16 = icmp ne i32 %15, 0
88    br i1 %16, label %vector.body, label %middle.block
89
90  middle.block:                                     ; preds = %vector.body
91    %17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)
92    br label %for.cond.cleanup
93
94  for.cond.cleanup:                                 ; preds = %middle.block, %entry
95    %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]
96    ret i32 %res.0.lcssa
97  }
98
99  define dso_local arm_aapcs_vfpcc i32 @mul_var_i16(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) {
100  entry:
101    %cmp9.not = icmp eq i32 %N, 0
102    %0 = add i32 %N, 3
103    %1 = lshr i32 %0, 2
104    %2 = shl nuw i32 %1, 2
105    %3 = add i32 %2, -4
106    %4 = lshr i32 %3, 2
107    %5 = add nuw nsw i32 %4, 1
108    br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph
109
110  vector.ph:                                        ; preds = %entry
111    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
112    br label %vector.body
113
114  vector.body:                                      ; preds = %vector.body, %vector.ph
115    %lsr.iv14 = phi ptr [ %scevgep15, %vector.body ], [ %b, %vector.ph ]
116    %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]
117    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]
118    %6 = phi i32 [ %start, %vector.ph ], [ %15, %vector.body ]
119    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
120    %lsr.iv13 = bitcast ptr %lsr.iv to ptr
121    %lsr.iv1416 = bitcast ptr %lsr.iv14 to ptr
122    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
123    %9 = sub i32 %7, 4
124    %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv13, i32 2, <4 x i1> %8, <4 x i16> undef)
125    %10 = sext <4 x i16> %wide.masked.load to <4 x i32>
126    %wide.masked.load12 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1416, i32 2, <4 x i1> %8, <4 x i16> undef)
127    %11 = sext <4 x i16> %wide.masked.load12 to <4 x i32>
128    %12 = mul nsw <4 x i32> %11, %10
129    %13 = select <4 x i1> %8, <4 x i32> %12, <4 x i32> zeroinitializer
130    %14 = add <4 x i32> %vec.phi, %13
131    %scevgep = getelementptr i16, ptr %lsr.iv, i32 4
132    %scevgep15 = getelementptr i16, ptr %lsr.iv14, i32 4
133    %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
134    %16 = icmp ne i32 %15, 0
135    br i1 %16, label %vector.body, label %middle.block
136
137  middle.block:                                     ; preds = %vector.body
138    %17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)
139    br label %for.cond.cleanup
140
141  for.cond.cleanup:                                 ; preds = %middle.block, %entry
142    %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]
143    ret i32 %res.0.lcssa
144  }
145
146  define dso_local arm_aapcs_vfpcc i32 @add_var_i16(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) {
147  entry:
148    %cmp10.not = icmp eq i32 %N, 0
149    %0 = add i32 %N, 3
150    %1 = lshr i32 %0, 2
151    %2 = shl nuw i32 %1, 2
152    %3 = add i32 %2, -4
153    %4 = lshr i32 %3, 2
154    %5 = add nuw nsw i32 %4, 1
155    br i1 %cmp10.not, label %for.cond.cleanup, label %vector.ph
156
157  vector.ph:                                        ; preds = %entry
158    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
159    br label %vector.body
160
161  vector.body:                                      ; preds = %vector.body, %vector.ph
162    %lsr.iv15 = phi ptr [ %scevgep16, %vector.body ], [ %b, %vector.ph ]
163    %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]
164    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]
165    %6 = phi i32 [ %start, %vector.ph ], [ %15, %vector.body ]
166    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
167    %lsr.iv14 = bitcast ptr %lsr.iv to ptr
168    %lsr.iv1517 = bitcast ptr %lsr.iv15 to ptr
169    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
170    %9 = sub i32 %7, 4
171    %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv14, i32 2, <4 x i1> %8, <4 x i16> undef)
172    %10 = sext <4 x i16> %wide.masked.load to <4 x i32>
173    %wide.masked.load13 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1517, i32 2, <4 x i1> %8, <4 x i16> undef)
174    %11 = sext <4 x i16> %wide.masked.load13 to <4 x i32>
175    %12 = add <4 x i32> %vec.phi, %10
176    %13 = add <4 x i32> %12, %11
177    %14 = select <4 x i1> %8, <4 x i32> %13, <4 x i32> %vec.phi
178    %scevgep = getelementptr i16, ptr %lsr.iv, i32 4
179    %scevgep16 = getelementptr i16, ptr %lsr.iv15, i32 4
180    %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
181    %16 = icmp ne i32 %15, 0
182    br i1 %16, label %vector.body, label %middle.block
183
184  middle.block:                                     ; preds = %vector.body
185    %17 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %14)
186    br label %for.cond.cleanup
187
188  for.cond.cleanup:                                 ; preds = %middle.block, %entry
189    %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]
190    ret i32 %res.0.lcssa
191  }
192
193  define dso_local arm_aapcs_vfpcc i32 @mul_var_i32(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
194  entry:
195    %cmp8.not = icmp eq i32 %N, 0
196    %0 = add i32 %N, 3
197    %1 = lshr i32 %0, 2
198    %2 = shl nuw i32 %1, 2
199    %3 = add i32 %2, -4
200    %4 = lshr i32 %3, 2
201    %5 = add nuw nsw i32 %4, 1
202    br i1 %cmp8.not, label %for.cond.cleanup, label %vector.ph
203
204  vector.ph:                                        ; preds = %entry
205    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
206    br label %vector.body
207
208  vector.body:                                      ; preds = %vector.body, %vector.ph
209    %lsr.iv13 = phi ptr [ %scevgep14, %vector.body ], [ %b, %vector.ph ]
210    %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]
211    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]
212    %6 = phi i32 [ %start, %vector.ph ], [ %13, %vector.body ]
213    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
214    %lsr.iv12 = bitcast ptr %lsr.iv to ptr
215    %lsr.iv1315 = bitcast ptr %lsr.iv13 to ptr
216    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
217    %9 = sub i32 %7, 4
218    %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv12, i32 4, <4 x i1> %8, <4 x i32> undef)
219    %wide.masked.load11 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1315, i32 4, <4 x i1> %8, <4 x i32> undef)
220    %10 = mul nsw <4 x i32> %wide.masked.load11, %wide.masked.load
221    %11 = select <4 x i1> %8, <4 x i32> %10, <4 x i32> zeroinitializer
222    %12 = add <4 x i32> %vec.phi, %11
223    %scevgep = getelementptr i32, ptr %lsr.iv, i32 4
224    %scevgep14 = getelementptr i32, ptr %lsr.iv13, i32 4
225    %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
226    %14 = icmp ne i32 %13, 0
227    br i1 %14, label %vector.body, label %middle.block
228
229  middle.block:                                     ; preds = %vector.body
230    %15 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %12)
231    br label %for.cond.cleanup
232
233  for.cond.cleanup:                                 ; preds = %middle.block, %entry
234    %res.0.lcssa = phi i32 [ 0, %entry ], [ %15, %middle.block ]
235    ret i32 %res.0.lcssa
236  }
237
238  define dso_local arm_aapcs_vfpcc i32 @add_var_i32(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
239  entry:
240    %cmp9.not = icmp eq i32 %N, 0
241    %0 = add i32 %N, 3
242    %1 = lshr i32 %0, 2
243    %2 = shl nuw i32 %1, 2
244    %3 = add i32 %2, -4
245    %4 = lshr i32 %3, 2
246    %5 = add nuw nsw i32 %4, 1
247    br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph
248
249  vector.ph:                                        ; preds = %entry
250    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
251    br label %vector.body
252
253  vector.body:                                      ; preds = %vector.body, %vector.ph
254    %lsr.iv14 = phi ptr [ %scevgep15, %vector.body ], [ %b, %vector.ph ]
255    %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ]
256    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]
257    %6 = phi i32 [ %start, %vector.ph ], [ %13, %vector.body ]
258    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
259    %lsr.iv13 = bitcast ptr %lsr.iv to ptr
260    %lsr.iv1416 = bitcast ptr %lsr.iv14 to ptr
261    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
262    %9 = sub i32 %7, 4
263    %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv13, i32 4, <4 x i1> %8, <4 x i32> undef)
264    %wide.masked.load12 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1416, i32 4, <4 x i1> %8, <4 x i32> undef)
265    %10 = add <4 x i32> %wide.masked.load, %vec.phi
266    %11 = add <4 x i32> %10, %wide.masked.load12
267    %12 = select <4 x i1> %8, <4 x i32> %11, <4 x i32> %vec.phi
268    %scevgep = getelementptr i32, ptr %lsr.iv, i32 4
269    %scevgep15 = getelementptr i32, ptr %lsr.iv14, i32 4
270    %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
271    %14 = icmp ne i32 %13, 0
272    br i1 %14, label %vector.body, label %middle.block
273
274  middle.block:                                     ; preds = %vector.body
275    %15 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %12)
276    br label %for.cond.cleanup
277
278  for.cond.cleanup:                                 ; preds = %middle.block, %entry
279    %res.0.lcssa = phi i32 [ 0, %entry ], [ %15, %middle.block ]
280    ret i32 %res.0.lcssa
281  }
282
283  declare <4 x i8> @llvm.masked.load.v4i8.p0(ptr, i32 immarg, <4 x i1>, <4 x i8>)
284  declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>)
285  declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)
286  declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
287  declare i32 @llvm.start.loop.iterations.i32(i32)
288  declare i32 @llvm.loop.decrement.reg.i32(i32, i32)
289  declare <4 x i1> @llvm.arm.mve.vctp32(i32)
290
291...
292---
293name:            mul_var_i8
294alignment:       2
295tracksRegLiveness: true
296registers:       []
297liveins:
298  - { reg: '$r0', virtual-reg: '' }
299  - { reg: '$r1', virtual-reg: '' }
300  - { reg: '$r2', virtual-reg: '' }
301frameInfo:
302  stackSize:       8
303  offsetAdjustment: 0
304  maxAlignment:    4
305fixedStack:      []
306stack:
307  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
308      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
309      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
310  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
311      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
312      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
313callSites:       []
314constants:       []
315machineFunctionInfo: {}
316body:             |
317  ; CHECK-LABEL: name: mul_var_i8
318  ; CHECK: bb.0.entry:
319  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
320  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2, $r7
321  ; CHECK-NEXT: {{  $}}
322  ; CHECK-NEXT:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
323  ; CHECK-NEXT:   t2IT 0, 4, implicit-def $itstate
324  ; CHECK-NEXT:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
325  ; CHECK-NEXT:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
326  ; CHECK-NEXT: {{  $}}
327  ; CHECK-NEXT: bb.1.vector.ph:
328  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
329  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2
330  ; CHECK-NEXT: {{  $}}
331  ; CHECK-NEXT:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
332  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
333  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -4
334  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r7, -8
335  ; CHECK-NEXT:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
336  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
337  ; CHECK-NEXT:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
338  ; CHECK-NEXT:   $lr = MVE_DLSTP_32 killed renamable $r2
339  ; CHECK-NEXT: {{  $}}
340  ; CHECK-NEXT: bb.2.vector.body (align 4):
341  ; CHECK-NEXT:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
342  ; CHECK-NEXT:   liveins: $lr, $q0, $r0, $r1
343  ; CHECK-NEXT: {{  $}}
344  ; CHECK-NEXT:   renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv13, align 1)
345  ; CHECK-NEXT:   renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv1416, align 1)
346  ; CHECK-NEXT:   renamable $q1 = nuw nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
347  ; CHECK-NEXT:   renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0
348  ; CHECK-NEXT:   $lr = MVE_LETP killed renamable $lr, %bb.2
349  ; CHECK-NEXT: {{  $}}
350  ; CHECK-NEXT: bb.3.middle.block:
351  ; CHECK-NEXT:   liveins: $q0
352  ; CHECK-NEXT: {{  $}}
353  ; CHECK-NEXT:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
354  ; CHECK-NEXT:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
355  bb.0.entry:
356    successors: %bb.1(0x50000000)
357    liveins: $r0, $r1, $r2, $lr
358
359    tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
360    t2IT 0, 4, implicit-def $itstate
361    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
362    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
363
364  bb.1.vector.ph:
365    successors: %bb.2(0x80000000)
366    liveins: $r0, $r1, $r2, $lr
367
368    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
369    frame-setup CFI_INSTRUCTION def_cfa_offset 8
370    frame-setup CFI_INSTRUCTION offset $lr, -4
371    frame-setup CFI_INSTRUCTION offset $r7, -8
372    $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
373    frame-setup CFI_INSTRUCTION def_cfa_register $r7
374    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
375    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
376    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
377    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
378    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
379    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
380    $lr = t2DoLoopStart renamable $lr
381
382  bb.2.vector.body (align 4):
383    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
384    liveins: $lr, $q0, $r0, $r1, $r2
385
386    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
387    MVE_VPST 4, implicit $vpr
388    renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s32) from %ir.lsr.iv13, align 1)
389    renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s32) from %ir.lsr.iv1416, align 1)
390    renamable $lr = t2LoopDec killed renamable $lr, 1
391    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
392    renamable $q1 = nuw nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
393    MVE_VPST 8, implicit $vpr
394    renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, renamable $q0
395    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
396    tB %bb.3, 14 /* CC::al */, $noreg
397
398  bb.3.middle.block:
399    liveins: $q0
400
401    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
402    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
403
404...
405---
406name:            add_var_i8
407alignment:       2
408tracksRegLiveness: true
409registers:       []
410liveins:
411  - { reg: '$r0', virtual-reg: '' }
412  - { reg: '$r1', virtual-reg: '' }
413  - { reg: '$r2', virtual-reg: '' }
414frameInfo:
415  stackSize:       8
416  offsetAdjustment: 0
417  maxAlignment:    4
418fixedStack:      []
419stack:
420  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
421      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
422      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
423  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
424      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
425      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
426callSites:       []
427constants:       []
428machineFunctionInfo: {}
429body:             |
430  ; CHECK-LABEL: name: add_var_i8
431  ; CHECK: bb.0.entry:
432  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
433  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2, $r7
434  ; CHECK-NEXT: {{  $}}
435  ; CHECK-NEXT:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
436  ; CHECK-NEXT:   t2IT 0, 4, implicit-def $itstate
437  ; CHECK-NEXT:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
438  ; CHECK-NEXT:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
439  ; CHECK-NEXT: {{  $}}
440  ; CHECK-NEXT: bb.1.vector.ph:
441  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
442  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2
443  ; CHECK-NEXT: {{  $}}
444  ; CHECK-NEXT:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
445  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
446  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -4
447  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r7, -8
448  ; CHECK-NEXT:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
449  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
450  ; CHECK-NEXT:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
451  ; CHECK-NEXT:   $lr = MVE_DLSTP_32 killed renamable $r2
452  ; CHECK-NEXT: {{  $}}
453  ; CHECK-NEXT: bb.2.vector.body (align 4):
454  ; CHECK-NEXT:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
455  ; CHECK-NEXT:   liveins: $lr, $q0, $r0, $r1
456  ; CHECK-NEXT: {{  $}}
457  ; CHECK-NEXT:   renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv14, align 1)
458  ; CHECK-NEXT:   renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv1517, align 1)
459  ; CHECK-NEXT:   renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
460  ; CHECK-NEXT:   renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0
461  ; CHECK-NEXT:   $lr = MVE_LETP killed renamable $lr, %bb.2
462  ; CHECK-NEXT: {{  $}}
463  ; CHECK-NEXT: bb.3.middle.block:
464  ; CHECK-NEXT:   liveins: $q0
465  ; CHECK-NEXT: {{  $}}
466  ; CHECK-NEXT:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
467  ; CHECK-NEXT:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
468  bb.0.entry:
469    successors: %bb.1(0x50000000)
470    liveins: $r0, $r1, $r2, $lr
471
472    tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
473    t2IT 0, 4, implicit-def $itstate
474    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
475    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
476
477  bb.1.vector.ph:
478    successors: %bb.2(0x80000000)
479    liveins: $r0, $r1, $r2, $lr
480
481    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
482    frame-setup CFI_INSTRUCTION def_cfa_offset 8
483    frame-setup CFI_INSTRUCTION offset $lr, -4
484    frame-setup CFI_INSTRUCTION offset $r7, -8
485    $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
486    frame-setup CFI_INSTRUCTION def_cfa_register $r7
487    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
488    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
489    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
490    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
491    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
492    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
493    $lr = t2DoLoopStart renamable $lr
494
495  bb.2.vector.body (align 4):
496    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
497    liveins: $lr, $q0, $r0, $r1, $r2
498
499    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
500    MVE_VPST 4, implicit $vpr
501    renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s32) from %ir.lsr.iv14, align 1)
502    renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s32) from %ir.lsr.iv1517, align 1)
503    renamable $lr = t2LoopDec killed renamable $lr, 1
504    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
505    renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
506    MVE_VPST 8, implicit $vpr
507    renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
508    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
509    tB %bb.3, 14 /* CC::al */, $noreg
510
511  bb.3.middle.block:
512    liveins: $q0
513
514    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
515    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
516
517...
518---
519name:            mul_var_i16
520alignment:       2
521exposesReturnsTwice: false
522tracksRegLiveness: true
523registers:       []
524liveins:
525  - { reg: '$r0', virtual-reg: '' }
526  - { reg: '$r1', virtual-reg: '' }
527  - { reg: '$r2', virtual-reg: '' }
528frameInfo:
529  stackSize:       8
530  offsetAdjustment: 0
531  maxAlignment:    4
532fixedStack:      []
533stack:
534  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
535      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
536      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
537  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
538      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
539      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
540callSites:       []
541constants:       []
542machineFunctionInfo: {}
543body:             |
544  ; CHECK-LABEL: name: mul_var_i16
545  ; CHECK: bb.0.entry:
546  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
547  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2, $r7
548  ; CHECK-NEXT: {{  $}}
549  ; CHECK-NEXT:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
550  ; CHECK-NEXT:   t2IT 0, 4, implicit-def $itstate
551  ; CHECK-NEXT:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
552  ; CHECK-NEXT:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
553  ; CHECK-NEXT: {{  $}}
554  ; CHECK-NEXT: bb.1.vector.ph:
555  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
556  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2
557  ; CHECK-NEXT: {{  $}}
558  ; CHECK-NEXT:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
559  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
560  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -4
561  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r7, -8
562  ; CHECK-NEXT:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
563  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
564  ; CHECK-NEXT:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
565  ; CHECK-NEXT:   $lr = MVE_DLSTP_32 killed renamable $r2
566  ; CHECK-NEXT: {{  $}}
567  ; CHECK-NEXT: bb.2.vector.body (align 4):
568  ; CHECK-NEXT:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
569  ; CHECK-NEXT:   liveins: $lr, $q0, $r0, $r1
570  ; CHECK-NEXT: {{  $}}
571  ; CHECK-NEXT:   renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv13, align 2)
572  ; CHECK-NEXT:   renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv1416, align 2)
573  ; CHECK-NEXT:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
574  ; CHECK-NEXT:   renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0
575  ; CHECK-NEXT:   $lr = MVE_LETP killed renamable $lr, %bb.2
576  ; CHECK-NEXT: {{  $}}
577  ; CHECK-NEXT: bb.3.middle.block:
578  ; CHECK-NEXT:   liveins: $q0
579  ; CHECK-NEXT: {{  $}}
580  ; CHECK-NEXT:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
581  ; CHECK-NEXT:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
582  bb.0.entry:
583    successors: %bb.1(0x50000000)
584    liveins: $r0, $r1, $r2, $lr
585
586    tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
587    t2IT 0, 4, implicit-def $itstate
588    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
589    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
590
591  bb.1.vector.ph:
592    successors: %bb.2(0x80000000)
593    liveins: $r0, $r1, $r2, $lr
594
595    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
596    frame-setup CFI_INSTRUCTION def_cfa_offset 8
597    frame-setup CFI_INSTRUCTION offset $lr, -4
598    frame-setup CFI_INSTRUCTION offset $r7, -8
599    $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
600    frame-setup CFI_INSTRUCTION def_cfa_register $r7
601    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
602    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
603    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
604    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
605    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
606    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
607    $lr = t2DoLoopStart renamable $lr
608
609  bb.2.vector.body (align 4):
610    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
611    liveins: $lr, $q0, $r0, $r1, $r2
612
613    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
614    MVE_VPST 4, implicit $vpr
615    renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv13, align 2)
616    renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1416, align 2)
617    renamable $lr = t2LoopDec killed renamable $lr, 1
618    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
619    renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
620    MVE_VPST 8, implicit $vpr
621    renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, renamable $q0
622    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
623    tB %bb.3, 14 /* CC::al */, $noreg
624
625  bb.3.middle.block:
626    liveins: $q0
627
628    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
629    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
630
631...
632---
633name:            add_var_i16
634alignment:       2
635tracksRegLiveness: true
636registers:       []
637liveins:
638  - { reg: '$r0', virtual-reg: '' }
639  - { reg: '$r1', virtual-reg: '' }
640  - { reg: '$r2', virtual-reg: '' }
641frameInfo:
642  stackSize:       8
643  offsetAdjustment: 0
644  maxAlignment:    4
645fixedStack:      []
646stack:
647  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
648      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
649      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
650  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
651      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
652      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
653callSites:       []
654constants:       []
655machineFunctionInfo: {}
656body:             |
657  ; CHECK-LABEL: name: add_var_i16
658  ; CHECK: bb.0.entry:
659  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
660  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2, $r7
661  ; CHECK-NEXT: {{  $}}
662  ; CHECK-NEXT:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
663  ; CHECK-NEXT:   t2IT 0, 4, implicit-def $itstate
664  ; CHECK-NEXT:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
665  ; CHECK-NEXT:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
666  ; CHECK-NEXT: {{  $}}
667  ; CHECK-NEXT: bb.1.vector.ph:
668  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
669  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2
670  ; CHECK-NEXT: {{  $}}
671  ; CHECK-NEXT:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
672  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
673  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -4
674  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r7, -8
675  ; CHECK-NEXT:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
676  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
677  ; CHECK-NEXT:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
678  ; CHECK-NEXT:   $lr = MVE_DLSTP_32 killed renamable $r2
679  ; CHECK-NEXT: {{  $}}
680  ; CHECK-NEXT: bb.2.vector.body (align 4):
681  ; CHECK-NEXT:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
682  ; CHECK-NEXT:   liveins: $lr, $q0, $r0, $r1
683  ; CHECK-NEXT: {{  $}}
684  ; CHECK-NEXT:   renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv14, align 2)
685  ; CHECK-NEXT:   renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv1517, align 2)
686  ; CHECK-NEXT:   renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
687  ; CHECK-NEXT:   renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0
688  ; CHECK-NEXT:   $lr = MVE_LETP killed renamable $lr, %bb.2
689  ; CHECK-NEXT: {{  $}}
690  ; CHECK-NEXT: bb.3.middle.block:
691  ; CHECK-NEXT:   liveins: $q0
692  ; CHECK-NEXT: {{  $}}
693  ; CHECK-NEXT:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
694  ; CHECK-NEXT:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
695  bb.0.entry:
696    successors: %bb.1(0x50000000)
697    liveins: $r0, $r1, $r2, $lr
698
699    tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
700    t2IT 0, 4, implicit-def $itstate
701    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
702    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
703
704  bb.1.vector.ph:
705    successors: %bb.2(0x80000000)
706    liveins: $r0, $r1, $r2, $lr
707
708    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
709    frame-setup CFI_INSTRUCTION def_cfa_offset 8
710    frame-setup CFI_INSTRUCTION offset $lr, -4
711    frame-setup CFI_INSTRUCTION offset $r7, -8
712    $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
713    frame-setup CFI_INSTRUCTION def_cfa_register $r7
714    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
715    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
716    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
717    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
718    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
719    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
720    $lr = t2DoLoopStart renamable $lr
721
722  bb.2.vector.body (align 4):
723    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
724    liveins: $lr, $q0, $r0, $r1, $r2
725
726    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
727    MVE_VPST 4, implicit $vpr
728    renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv14, align 2)
729    renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1517, align 2)
730    renamable $lr = t2LoopDec killed renamable $lr, 1
731    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
732    renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
733    MVE_VPST 8, implicit $vpr
734    renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
735    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
736    tB %bb.3, 14 /* CC::al */, $noreg
737
738  bb.3.middle.block:
739    liveins: $q0
740
741    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
742    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
743
744...
745---
746name:            mul_var_i32
747alignment:       2
748tracksRegLiveness: true
749registers:       []
750liveins:
751  - { reg: '$r0', virtual-reg: '' }
752  - { reg: '$r1', virtual-reg: '' }
753  - { reg: '$r2', virtual-reg: '' }
754frameInfo:
755  stackSize:       8
756  offsetAdjustment: 0
757  maxAlignment:    4
758fixedStack:      []
759stack:
760  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
761      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
762      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
763  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
764      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
765      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
766callSites:       []
767constants:       []
768machineFunctionInfo: {}
769body:             |
770  ; CHECK-LABEL: name: mul_var_i32
771  ; CHECK: bb.0.entry:
772  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
773  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2, $r7
774  ; CHECK-NEXT: {{  $}}
775  ; CHECK-NEXT:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
776  ; CHECK-NEXT:   t2IT 0, 4, implicit-def $itstate
777  ; CHECK-NEXT:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
778  ; CHECK-NEXT:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
779  ; CHECK-NEXT: {{  $}}
780  ; CHECK-NEXT: bb.1.vector.ph:
781  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
782  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2
783  ; CHECK-NEXT: {{  $}}
784  ; CHECK-NEXT:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
785  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
786  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -4
787  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r7, -8
788  ; CHECK-NEXT:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
789  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
790  ; CHECK-NEXT:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
791  ; CHECK-NEXT:   $lr = MVE_DLSTP_32 killed renamable $r2
792  ; CHECK-NEXT: {{  $}}
793  ; CHECK-NEXT: bb.2.vector.body (align 4):
794  ; CHECK-NEXT:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
795  ; CHECK-NEXT:   liveins: $lr, $q0, $r0, $r1
796  ; CHECK-NEXT: {{  $}}
797  ; CHECK-NEXT:   renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv12, align 4)
798  ; CHECK-NEXT:   renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1315, align 4)
799  ; CHECK-NEXT:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
800  ; CHECK-NEXT:   renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0
801  ; CHECK-NEXT:   $lr = MVE_LETP killed renamable $lr, %bb.2
802  ; CHECK-NEXT: {{  $}}
803  ; CHECK-NEXT: bb.3.middle.block:
804  ; CHECK-NEXT:   liveins: $q0
805  ; CHECK-NEXT: {{  $}}
806  ; CHECK-NEXT:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
807  ; CHECK-NEXT:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
808  bb.0.entry:
809    successors: %bb.1(0x50000000)
810    liveins: $r0, $r1, $r2, $lr
811
812    tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
813    t2IT 0, 4, implicit-def $itstate
814    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
815    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
816
817  bb.1.vector.ph:
818    successors: %bb.2(0x80000000)
819    liveins: $r0, $r1, $r2, $lr
820
821    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
822    frame-setup CFI_INSTRUCTION def_cfa_offset 8
823    frame-setup CFI_INSTRUCTION offset $lr, -4
824    frame-setup CFI_INSTRUCTION offset $r7, -8
825    $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
826    frame-setup CFI_INSTRUCTION def_cfa_register $r7
827    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
828    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
829    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
830    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
831    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
832    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
833    $lr = t2DoLoopStart renamable $lr
834
835  bb.2.vector.body (align 4):
836    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
837    liveins: $lr, $q0, $r0, $r1, $r2
838
839    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
840    MVE_VPST 4, implicit $vpr
841    renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv12, align 4)
842    renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1315, align 4)
843    renamable $lr = t2LoopDec killed renamable $lr, 1
844    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
845    renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
846    MVE_VPST 8, implicit $vpr
847    renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, renamable $q0
848    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
849    tB %bb.3, 14 /* CC::al */, $noreg
850
851  bb.3.middle.block:
852    liveins: $q0
853
854    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
855    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
856
857...
858---
859name:            add_var_i32
860alignment:       2
861tracksRegLiveness: true
862registers:       []
863liveins:
864  - { reg: '$r0', virtual-reg: '' }
865  - { reg: '$r1', virtual-reg: '' }
866  - { reg: '$r2', virtual-reg: '' }
867frameInfo:
868  stackSize:       8
869  offsetAdjustment: 0
870  maxAlignment:    4
871fixedStack:      []
872stack:
873  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
874      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
875      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
876  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
877      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
878      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
879callSites:       []
880constants:       []
881machineFunctionInfo: {}
882body:             |
883  ; CHECK-LABEL: name: add_var_i32
884  ; CHECK: bb.0.entry:
885  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
886  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2, $r7
887  ; CHECK-NEXT: {{  $}}
888  ; CHECK-NEXT:   tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
889  ; CHECK-NEXT:   t2IT 0, 4, implicit-def $itstate
890  ; CHECK-NEXT:   renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
891  ; CHECK-NEXT:   tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
892  ; CHECK-NEXT: {{  $}}
893  ; CHECK-NEXT: bb.1.vector.ph:
894  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
895  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2
896  ; CHECK-NEXT: {{  $}}
897  ; CHECK-NEXT:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
898  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
899  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -4
900  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r7, -8
901  ; CHECK-NEXT:   dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
902  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
903  ; CHECK-NEXT:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
904  ; CHECK-NEXT:   $lr = MVE_DLSTP_32 killed renamable $r2
905  ; CHECK-NEXT: {{  $}}
906  ; CHECK-NEXT: bb.2.vector.body (align 4):
907  ; CHECK-NEXT:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
908  ; CHECK-NEXT:   liveins: $lr, $q0, $r0, $r1
909  ; CHECK-NEXT: {{  $}}
910  ; CHECK-NEXT:   renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
911  ; CHECK-NEXT:   renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
912  ; CHECK-NEXT:   renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
913  ; CHECK-NEXT:   renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0
914  ; CHECK-NEXT:   $lr = MVE_LETP killed renamable $lr, %bb.2
915  ; CHECK-NEXT: {{  $}}
916  ; CHECK-NEXT: bb.3.middle.block:
917  ; CHECK-NEXT:   liveins: $q0
918  ; CHECK-NEXT: {{  $}}
919  ; CHECK-NEXT:   renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
920  ; CHECK-NEXT:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
921  bb.0.entry:
922    successors: %bb.1(0x50000000)
923    liveins: $r0, $r1, $r2, $lr
924
925    tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
926    t2IT 0, 4, implicit-def $itstate
927    renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
928    tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
929
930  bb.1.vector.ph:
931    successors: %bb.2(0x80000000)
932    liveins: $r0, $r1, $r2, $lr
933
934    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
935    frame-setup CFI_INSTRUCTION def_cfa_offset 8
936    frame-setup CFI_INSTRUCTION offset $lr, -4
937    frame-setup CFI_INSTRUCTION offset $r7, -8
938    $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
939    frame-setup CFI_INSTRUCTION def_cfa_register $r7
940    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
941    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
942    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
943    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
944    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
945    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
946    $lr = t2DoLoopStart renamable $lr
947
948  bb.2.vector.body (align 4):
949    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
950    liveins: $lr, $q0, $r0, $r1, $r2
951
952    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
953    MVE_VPST 4, implicit $vpr
954    renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
955    renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
956    renamable $lr = t2LoopDec killed renamable $lr, 1
957    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
958    renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
959    MVE_VPST 8, implicit $vpr
960    renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
961    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
962    tB %bb.3, 14 /* CC::al */, $noreg
963
964  bb.3.middle.block:
965    liveins: $q0
966
967    renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
968    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
969
970...
971