1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -O3 -tail-predication=force-enabled-no-reductions %s -o - | FileCheck %s 3 4define arm_aapcs_vfpcc <4 x float> @arm_max_no_idx_f32_mve(ptr %pSrc, i32 %blockSize, ptr nocapture %pResult) { 5; CHECK-LABEL: arm_max_no_idx_f32_mve: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: .save {r7, lr} 8; CHECK-NEXT: push {r7, lr} 9; CHECK-NEXT: subs r2, r1, #4 10; CHECK-NEXT: movw r3, #0 11; CHECK-NEXT: movt r3, #65408 12; CHECK-NEXT: vdup.32 q0, r3 13; CHECK-NEXT: dlstp.32 lr, r1 14; CHECK-NEXT: .LBB0_1: @ %do.body 15; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 16; CHECK-NEXT: vldrw.u32 q1, [r0], #16 17; CHECK-NEXT: vmaxnm.f32 q0, q1, q0 18; CHECK-NEXT: letp lr, .LBB0_1 19; CHECK-NEXT: @ %bb.2: @ %do.end 20; CHECK-NEXT: pop {r7, pc} 21entry: 22 br label %do.body 23 24do.body: ; preds = %do.body, %entry 25 %blockSize.addr.0 = phi i32 [ %blockSize, %entry ], [ %sub, %do.body ] 26 %curExtremValVec.0 = phi <4 x float> [ <float 0xFFF0000000000000, float 0xFFF0000000000000, float 0xFFF0000000000000, float 0xFFF0000000000000>, %entry ], [ %3, %do.body ] 27 %pSrc.addr.0 = phi ptr [ %pSrc, %entry ], [ %add.ptr, %do.body ] 28 %0 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blockSize.addr.0) 29 %1 = bitcast ptr %pSrc.addr.0 to ptr 30 %2 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr %1, i32 4, <4 x i1> %0, <4 x float> zeroinitializer) 31 %3 = tail call fast <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %2, <4 x float> %curExtremValVec.0, i32 0, <4 x i1> %0, <4 x float> %curExtremValVec.0) 32 %add.ptr = getelementptr inbounds float, ptr %pSrc.addr.0, i32 4 33 %sub = add i32 %blockSize.addr.0, -4 34 %cmp = icmp sgt i32 %sub, 0 35 br i1 %cmp, label %do.body, label %do.end 36 37do.end: ; preds = %do.body 38 ret <4 x float> %3 39} 40 41declare <4 x i1> @llvm.arm.mve.vctp32(i32) 42 43declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>) 44 45declare <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) 46