1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s 3 4--- | 5 define dso_local arm_aapcs_vfpcc void @non_masked_store(ptr noalias nocapture %res, ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) { 6 entry: 7 %cmp10 = icmp eq i32 %N, 0 8 %0 = add i32 %N, 15 9 %1 = lshr i32 %0, 4 10 %2 = shl nuw i32 %1, 4 11 %3 = add i32 %2, -16 12 %4 = lshr i32 %3, 4 13 %5 = add nuw nsw i32 %4, 1 14 br i1 %cmp10, label %for.cond.cleanup, label %vector.ph 15 16 vector.ph: ; preds = %entry 17 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 18 br label %vector.body 19 20 vector.body: ; preds = %vector.body, %vector.ph 21 %lsr.iv19 = phi ptr [ %scevgep20, %vector.body ], [ %res, %vector.ph ] 22 %lsr.iv16 = phi ptr [ %scevgep17, %vector.body ], [ %b, %vector.ph ] 23 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 24 %6 = phi i32 [ %start, %vector.ph ], [ %11, %vector.body ] 25 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ] 26 %lsr.iv1921 = bitcast ptr %lsr.iv19 to ptr 27 %lsr.iv1618 = bitcast ptr %lsr.iv16 to ptr 28 %lsr.iv15 = bitcast ptr %lsr.iv to ptr 29 %8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %7) 30 %9 = sub i32 %7, 16 31 %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv15, i32 1, <16 x i1> %8, <16 x i8> undef) 32 %wide.masked.load14 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %lsr.iv1618, i32 1, <16 x i1> %8, <16 x i8> undef) 33 %10 = add <16 x i8> %wide.masked.load14, %wide.masked.load 34 store <16 x i8> %10, ptr %lsr.iv1921 35 %scevgep = getelementptr i8, ptr %lsr.iv, i32 16 36 %scevgep17 = getelementptr i8, ptr %lsr.iv16, i32 16 37 %scevgep20 = getelementptr i8, ptr %lsr.iv19, i32 16 38 %11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 39 %12 = icmp ne i32 %11, 0 40 br i1 %12, label %vector.body, label %for.cond.cleanup 41 42 for.cond.cleanup: ; preds = %vector.body, %entry 43 ret void 44 } 45 46 declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr, i32 immarg, <16 x i1>, <16 x i8>) 47 declare void @llvm.masked.store.v16i8.p0(<16 x i8>, ptr, i32 immarg, <16 x i1>) 48 declare i32 @llvm.start.loop.iterations.i32(i32) 49 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 50 declare <16 x i1> @llvm.arm.mve.vctp8(i32) 51 52... 53--- 54name: non_masked_store 55alignment: 2 56exposesReturnsTwice: false 57legalized: false 58regBankSelected: false 59selected: false 60failedISel: false 61tracksRegLiveness: true 62hasWinCFI: false 63registers: [] 64liveins: 65 - { reg: '$r0', virtual-reg: '' } 66 - { reg: '$r1', virtual-reg: '' } 67 - { reg: '$r2', virtual-reg: '' } 68 - { reg: '$r3', virtual-reg: '' } 69frameInfo: 70 isFrameAddressTaken: false 71 isReturnAddressTaken: false 72 hasStackMap: false 73 hasPatchPoint: false 74 stackSize: 8 75 offsetAdjustment: 0 76 maxAlignment: 4 77 adjustsStack: false 78 hasCalls: false 79 stackProtector: '' 80 maxCallFrameSize: 0 81 cvBytesOfCalleeSavedRegisters: 0 82 hasOpaqueSPAdjustment: false 83 hasVAStart: false 84 hasMustTailInVarArgFunc: false 85 localFrameSize: 0 86 savePoint: '' 87 restorePoint: '' 88fixedStack: [] 89stack: 90 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 91 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 92 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 93 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 94 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 95 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 96callSites: [] 97constants: [] 98machineFunctionInfo: {} 99body: | 100 ; CHECK-LABEL: name: non_masked_store 101 ; CHECK: bb.0.entry: 102 ; CHECK-NEXT: successors: %bb.1(0x80000000) 103 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 104 ; CHECK-NEXT: {{ $}} 105 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 106 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 107 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 108 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 109 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 110 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 111 ; CHECK-NEXT: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 112 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 113 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 114 ; CHECK-NEXT: {{ $}} 115 ; CHECK-NEXT: bb.1.vector.ph: 116 ; CHECK-NEXT: successors: %bb.2(0x80000000) 117 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 118 ; CHECK-NEXT: {{ $}} 119 ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg 120 ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg 121 ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 15, 14 /* CC::al */, $noreg, $noreg 122 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg 123 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg 124 ; CHECK-NEXT: {{ $}} 125 ; CHECK-NEXT: bb.2.vector.body: 126 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 127 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 128 ; CHECK-NEXT: {{ $}} 129 ; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg 130 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg 131 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr 132 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv15, align 1) 133 ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1618, align 1) 134 ; CHECK-NEXT: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 135 ; CHECK-NEXT: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg, $noreg :: (store (s128) into %ir.lsr.iv1921, align 1) 136 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 137 ; CHECK-NEXT: {{ $}} 138 ; CHECK-NEXT: bb.3.for.cond.cleanup: 139 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 140 bb.0.entry: 141 successors: %bb.1(0x80000000) 142 liveins: $r0, $r1, $r2, $r3, $lr 143 144 frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp 145 frame-setup CFI_INSTRUCTION def_cfa_offset 8 146 frame-setup CFI_INSTRUCTION offset $lr, -4 147 frame-setup CFI_INSTRUCTION offset $r7, -8 148 $r7 = frame-setup tMOVr $sp, 14, $noreg 149 frame-setup CFI_INSTRUCTION def_cfa_register $r7 150 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr 151 t2IT 0, 8, implicit-def $itstate 152 tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate 153 154 bb.1.vector.ph: 155 successors: %bb.2(0x80000000) 156 liveins: $r0, $r1, $r2, $r3, $lr 157 158 renamable $r12 = t2ADDri renamable $r3, 15, 14, $noreg, $noreg 159 renamable $lr = t2MOVi 1, 14, $noreg, $noreg 160 renamable $r12 = t2BICri killed renamable $r12, 15, 14, $noreg, $noreg 161 renamable $r12 = t2SUBri killed renamable $r12, 16, 14, $noreg, $noreg 162 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14, $noreg, $noreg 163 $lr = t2DoLoopStart renamable $lr 164 165 bb.2.vector.body: 166 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 167 liveins: $lr, $r0, $r1, $r2, $r3 168 169 renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg 170 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg 171 MVE_VPST 4, implicit $vpr 172 renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv15, align 1) 173 renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1618, align 1) 174 renamable $lr = t2LoopDec killed renamable $lr, 1 175 renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 176 renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg, $noreg :: (store (s128) into %ir.lsr.iv1921, align 1) 177 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 178 tB %bb.3, 14, $noreg 179 180 bb.3.for.cond.cleanup: 181 tPOP_RET 14, $noreg, def $r7, def $pc 182 183... 184