1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3--- | 4 define dso_local i32 @no_vpsel_liveout(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 { 5 entry: 6 %cmp9 = icmp eq i32 %N, 0 7 %tmp = add i32 %N, 3 8 %tmp1 = lshr i32 %tmp, 2 9 %tmp2 = shl nuw i32 %tmp1, 2 10 %tmp3 = add i32 %tmp2, -4 11 %tmp4 = lshr i32 %tmp3, 2 12 %tmp5 = add nuw nsw i32 %tmp4, 1 13 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph 14 15 vector.ph: ; preds = %entry 16 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 17 br label %vector.body 18 19 vector.body: ; preds = %vector.body, %vector.ph 20 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 21 %lsr.iv18 = phi ptr [ %scevgep19, %vector.body ], [ %b, %vector.ph ] 22 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 23 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp13, %vector.body ] 24 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 25 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 26 %lsr.iv1820 = bitcast ptr %lsr.iv18 to ptr 27 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 28 %tmp9 = sub i32 %tmp7, 4 29 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 30 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> 31 %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1820, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 32 %tmp11 = sext <4 x i16> %wide.masked.load14 to <4 x i32> 33 %tmp12 = mul nsw <4 x i32> %tmp11, %tmp10 34 %tmp13 = add <4 x i32> %tmp12, %vec.phi 35 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4 36 %scevgep19 = getelementptr i16, ptr %lsr.iv18, i32 4 37 %tmp14 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 38 %tmp15 = icmp ne i32 %tmp14, 0 39 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 40 br i1 %tmp15, label %vector.body, label %middle.block 41 42 middle.block: ; preds = %vector.body 43 %tmp16 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp13) 44 br label %for.cond.cleanup 45 46 for.cond.cleanup: ; preds = %middle.block, %entry 47 %res.0.lcssa = phi i32 [ 0, %entry ], [ %tmp16, %middle.block ] 48 ret i32 %res.0.lcssa 49 } 50 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>) #1 51 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #2 52 declare i32 @llvm.start.loop.iterations.i32(i32) #3 53 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3 54 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4 55 56... 57--- 58name: no_vpsel_liveout 59alignment: 2 60exposesReturnsTwice: false 61legalized: false 62regBankSelected: false 63selected: false 64failedISel: false 65tracksRegLiveness: true 66hasWinCFI: false 67registers: [] 68liveins: 69 - { reg: '$r0', virtual-reg: '' } 70 - { reg: '$r1', virtual-reg: '' } 71 - { reg: '$r2', virtual-reg: '' } 72frameInfo: 73 isFrameAddressTaken: false 74 isReturnAddressTaken: false 75 hasStackMap: false 76 hasPatchPoint: false 77 stackSize: 8 78 offsetAdjustment: 0 79 maxAlignment: 4 80 adjustsStack: false 81 hasCalls: false 82 stackProtector: '' 83 maxCallFrameSize: 0 84 cvBytesOfCalleeSavedRegisters: 0 85 hasOpaqueSPAdjustment: false 86 hasVAStart: false 87 hasMustTailInVarArgFunc: false 88 localFrameSize: 0 89 savePoint: '' 90 restorePoint: '' 91fixedStack: [] 92stack: 93 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 94 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 95 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 96 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 97 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 98 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 99callSites: [] 100constants: [] 101machineFunctionInfo: {} 102body: | 103 ; CHECK-LABEL: name: no_vpsel_liveout 104 ; CHECK: bb.0.entry: 105 ; CHECK-NEXT: successors: %bb.1(0x80000000) 106 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 107 ; CHECK-NEXT: {{ $}} 108 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 109 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate 110 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate 111 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate 112 ; CHECK-NEXT: {{ $}} 113 ; CHECK-NEXT: bb.1.vector.ph: 114 ; CHECK-NEXT: successors: %bb.2(0x80000000) 115 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 116 ; CHECK-NEXT: {{ $}} 117 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 118 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 119 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 120 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 121 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 122 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 123 ; CHECK-NEXT: {{ $}} 124 ; CHECK-NEXT: bb.2.vector.body: 125 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 126 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1 127 ; CHECK-NEXT: {{ $}} 128 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 129 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) 130 ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 131 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 132 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 133 ; CHECK-NEXT: {{ $}} 134 ; CHECK-NEXT: bb.3.middle.block: 135 ; CHECK-NEXT: liveins: $q0 136 ; CHECK-NEXT: {{ $}} 137 ; CHECK-NEXT: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg 138 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 139 bb.0.entry: 140 successors: %bb.1(0x80000000) 141 liveins: $r0, $r1, $r2, $lr, $r7 142 143 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr 144 t2IT 0, 4, implicit-def $itstate 145 renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate 146 tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate 147 148 bb.1.vector.ph: 149 successors: %bb.2(0x80000000) 150 liveins: $r0, $r1, $r2, $lr, $r7 151 152 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 153 frame-setup CFI_INSTRUCTION def_cfa_offset 8 154 frame-setup CFI_INSTRUCTION offset $lr, -4 155 frame-setup CFI_INSTRUCTION offset $r7, -8 156 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg 157 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 158 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg 159 renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg 160 renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg 161 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg 162 $lr = t2DoLoopStart renamable $r12 163 $r3 = tMOVr killed $r12, 14, $noreg 164 165 bb.2.vector.body: 166 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 167 liveins: $q0, $r0, $r1, $r2, $r3 168 169 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 170 MVE_VPST 4, implicit $vpr 171 renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 172 renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) 173 $lr = tMOVr $r3, 14, $noreg 174 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 175 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg 176 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 177 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 178 renamable $lr = t2LoopDec killed renamable $lr, 1 179 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 180 tB %bb.3, 14, $noreg 181 182 bb.3.middle.block: 183 liveins: $q0 184 185 renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg 186 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 187 188... 189