1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-cp-islands %s -o - --verify-machineinstrs | FileCheck %s 3 4--- | 5 %struct.head_s = type { ptr, ptr } 6 %struct.data_s = type { i16, i16 } 7 8 define dso_local arm_aapcscc ptr @search(ptr readonly %list, ptr nocapture readonly %info) local_unnamed_addr { 9 entry: 10 %idx = getelementptr inbounds %struct.data_s, ptr %info, i32 0, i32 1 11 %tmp = load i16, ptr %idx, align 2 12 %cmp = icmp sgt i16 %tmp, -1 13 br i1 %cmp, label %while.cond.preheader, label %while.cond9.preheader 14 15 while.cond9.preheader: ; preds = %entry 16 %0 = icmp eq ptr %list, null 17 br i1 %0, label %return, label %land.rhs11.lr.ph 18 19 land.rhs11.lr.ph: ; preds = %while.cond9.preheader 20 %data16143 = bitcast ptr %info to ptr 21 %tmp1 = load i16, ptr %data16143, align 2 22 %conv15 = sext i16 %tmp1 to i32 23 br label %land.rhs11 24 25 while.cond.preheader: ; preds = %entry 26 %1 = icmp eq ptr %list, null 27 br i1 %1, label %return, label %land.rhs.preheader 28 29 land.rhs.preheader: ; preds = %while.cond.preheader 30 br label %land.rhs 31 32 while.body: ; preds = %land.rhs 33 %next4 = bitcast ptr %list.addr.033 to ptr 34 %tmp4 = load ptr, ptr %next4, align 4 35 %tobool = icmp eq ptr %tmp4, null 36 br i1 %tobool, label %return, label %land.rhs 37 38 land.rhs: ; preds = %land.rhs.preheader, %while.body 39 %list.addr.033 = phi ptr [ %tmp4, %while.body ], [ %list, %land.rhs.preheader ] 40 %info2 = getelementptr inbounds %struct.head_s, ptr %list.addr.033, i32 0, i32 1 41 %tmp2 = load ptr, ptr %info2, align 4 42 %idx3 = getelementptr inbounds %struct.data_s, ptr %tmp2, i32 0, i32 1 43 %tmp3 = load i16, ptr %idx3, align 2 44 %cmp7 = icmp eq i16 %tmp3, %tmp 45 br i1 %cmp7, label %return, label %while.body 46 47 while.body19: ; preds = %land.rhs11 48 %next205 = bitcast ptr %list.addr.136 to ptr 49 %tmp8 = load ptr, ptr %next205, align 4 50 %tobool10 = icmp eq ptr %tmp8, null 51 br i1 %tobool10, label %return, label %land.rhs11 52 53 land.rhs11: ; preds = %while.body19, %land.rhs11.lr.ph 54 %list.addr.136 = phi ptr [ %list, %land.rhs11.lr.ph ], [ %tmp8, %while.body19 ] 55 %info12 = getelementptr inbounds %struct.head_s, ptr %list.addr.136, i32 0, i32 1 56 %tmp5 = load ptr, ptr %info12, align 4 57 %data166 = bitcast ptr %tmp5 to ptr 58 %tmp6 = load i16, ptr %data166, align 2 59 %2 = and i16 %tmp6, 255 60 %and = zext i16 %2 to i32 61 %cmp16 = icmp eq i32 %and, %conv15 62 br i1 %cmp16, label %return, label %while.body19 63 64 return: ; preds = %land.rhs11, %while.body19, %land.rhs, %while.body, %while.cond.preheader, %while.cond9.preheader 65 %retval.0 = phi ptr [ null, %while.cond.preheader ], [ null, %while.cond9.preheader ], [ null, %while.body ], [ %list.addr.033, %land.rhs ], [ null, %while.body19 ], [ %list.addr.136, %land.rhs11 ] 66 ret ptr %retval.0 67 } 68 69... 70--- 71name: search 72alignment: 2 73exposesReturnsTwice: false 74legalized: false 75regBankSelected: false 76selected: false 77failedISel: false 78tracksRegLiveness: true 79hasWinCFI: false 80registers: [] 81liveins: 82 - { reg: '$r0', virtual-reg: '' } 83 - { reg: '$r1', virtual-reg: '' } 84frameInfo: 85 isFrameAddressTaken: false 86 isReturnAddressTaken: false 87 hasStackMap: false 88 hasPatchPoint: false 89 stackSize: 0 90 offsetAdjustment: 0 91 maxAlignment: 1 92 adjustsStack: false 93 hasCalls: false 94 stackProtector: '' 95 maxCallFrameSize: 0 96 cvBytesOfCalleeSavedRegisters: 0 97 hasOpaqueSPAdjustment: false 98 hasVAStart: false 99 hasMustTailInVarArgFunc: false 100 localFrameSize: 0 101 savePoint: '' 102 restorePoint: '' 103fixedStack: [] 104stack: [] 105callSites: [] 106constants: [] 107machineFunctionInfo: {} 108body: | 109 ; CHECK-LABEL: name: search 110 ; CHECK: bb.0.entry: 111 ; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.6(0x30000000) 112 ; CHECK-NEXT: liveins: $r0, $r1 113 ; CHECK-NEXT: {{ $}} 114 ; CHECK-NEXT: renamable $r2 = t2LDRSHi12 renamable $r1, 2, 14 /* CC::al */, $noreg :: (load (s16) from %ir.idx) 115 ; CHECK-NEXT: t2CMPri renamable $r2, -1, 14 /* CC::al */, $noreg, implicit-def $cpsr 116 ; CHECK-NEXT: tBcc %bb.6, 13 /* CC::le */, killed $cpsr 117 ; CHECK-NEXT: {{ $}} 118 ; CHECK-NEXT: bb.1.while.cond.preheader: 119 ; CHECK-NEXT: successors: %bb.2(0x80000000) 120 ; CHECK-NEXT: liveins: $r0, $r2 121 ; CHECK-NEXT: {{ $}} 122 ; CHECK-NEXT: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 123 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate 124 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate 125 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate 126 ; CHECK-NEXT: tB %bb.2, 14 /* CC::al */, $noreg 127 ; CHECK-NEXT: {{ $}} 128 ; CHECK-NEXT: bb.2: 129 ; CHECK-NEXT: successors: %bb.3(0x80000000) 130 ; CHECK-NEXT: liveins: $r0, $r2 131 ; CHECK-NEXT: {{ $}} 132 ; CHECK-NEXT: renamable $r1 = tUXTH killed renamable $r2, 14 /* CC::al */, $noreg 133 ; CHECK-NEXT: {{ $}} 134 ; CHECK-NEXT: bb.3.land.rhs: 135 ; CHECK-NEXT: successors: %bb.5(0x04000000), %bb.4(0x7c000000) 136 ; CHECK-NEXT: liveins: $r0, $r1 137 ; CHECK-NEXT: {{ $}} 138 ; CHECK-NEXT: renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.info2) 139 ; CHECK-NEXT: renamable $r2 = tLDRHi killed renamable $r2, 1, 14 /* CC::al */, $noreg :: (load (s16) from %ir.idx3) 140 ; CHECK-NEXT: tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr 141 ; CHECK-NEXT: tBcc %bb.5, 0 /* CC::eq */, killed $cpsr 142 ; CHECK-NEXT: {{ $}} 143 ; CHECK-NEXT: bb.4.while.body: 144 ; CHECK-NEXT: successors: %bb.3(0x80000000) 145 ; CHECK-NEXT: liveins: $r0, $r1 146 ; CHECK-NEXT: {{ $}} 147 ; CHECK-NEXT: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.next4) 148 ; CHECK-NEXT: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 149 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate 150 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate 151 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate 152 ; CHECK-NEXT: tB %bb.3, 14 /* CC::al */, $noreg 153 ; CHECK-NEXT: {{ $}} 154 ; CHECK-NEXT: bb.5.return: 155 ; CHECK-NEXT: liveins: $r0 156 ; CHECK-NEXT: {{ $}} 157 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0 158 ; CHECK-NEXT: {{ $}} 159 ; CHECK-NEXT: bb.6.while.cond9.preheader: 160 ; CHECK-NEXT: successors: %bb.7(0x80000000) 161 ; CHECK-NEXT: liveins: $r0, $r1 162 ; CHECK-NEXT: {{ $}} 163 ; CHECK-NEXT: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 164 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate 165 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate 166 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate 167 ; CHECK-NEXT: tB %bb.7, 14 /* CC::al */, $noreg 168 ; CHECK-NEXT: {{ $}} 169 ; CHECK-NEXT: bb.7.land.rhs11.lr.ph: 170 ; CHECK-NEXT: successors: %bb.8(0x80000000) 171 ; CHECK-NEXT: liveins: $r0, $r1 172 ; CHECK-NEXT: {{ $}} 173 ; CHECK-NEXT: renamable $r1 = t2LDRSHi12 killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (load (s16) from %ir.data16143) 174 ; CHECK-NEXT: {{ $}} 175 ; CHECK-NEXT: bb.8.land.rhs11: 176 ; CHECK-NEXT: successors: %bb.9(0x80000000) 177 ; CHECK-NEXT: liveins: $r0, $r1 178 ; CHECK-NEXT: {{ $}} 179 ; CHECK-NEXT: renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.info12) 180 ; CHECK-NEXT: renamable $r2 = tLDRBi killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (load (s8) from %ir.data166, align 2) 181 ; CHECK-NEXT: tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr 182 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 183 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate 184 ; CHECK-NEXT: tB %bb.9, 14 /* CC::al */, $noreg 185 ; CHECK-NEXT: {{ $}} 186 ; CHECK-NEXT: bb.9.while.body19: 187 ; CHECK-NEXT: successors: %bb.8(0x80000000) 188 ; CHECK-NEXT: liveins: $r0, $r1 189 ; CHECK-NEXT: {{ $}} 190 ; CHECK-NEXT: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.next205) 191 ; CHECK-NEXT: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 192 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate 193 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate 194 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate 195 ; CHECK-NEXT: tB %bb.8, 14 /* CC::al */, $noreg 196 bb.0.entry: 197 successors: %bb.2(0x50000000), %bb.1(0x30000000) 198 liveins: $r0, $r1 199 200 renamable $r2 = t2LDRSHi12 renamable $r1, 2, 14 /* CC::al */, $noreg :: (load (s16) from %ir.idx) 201 t2CMPri renamable $r2, -1, 14 /* CC::al */, $noreg, implicit-def $cpsr 202 t2Bcc %bb.1, 13 /* CC::le */, killed $cpsr 203 204 bb.2.while.cond.preheader: 205 successors: %bb.3(0x50000000) 206 liveins: $r0, $r2 207 208 tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 209 t2IT 0, 4, implicit-def $itstate 210 renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate 211 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate 212 t2B %bb.3, 14 /* CC::al */, $noreg 213 214 bb.3: 215 successors: %bb.4(0x80000000) 216 liveins: $r0, $r2 217 218 renamable $r1 = tUXTH killed renamable $r2, 14 /* CC::al */, $noreg 219 220 bb.4.land.rhs: 221 successors: %bb.9(0x04000000), %bb.5(0x7c000000) 222 liveins: $r0, $r1 223 224 renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.info2) 225 renamable $r2 = tLDRHi killed renamable $r2, 1, 14 /* CC::al */, $noreg :: (load (s16) from %ir.idx3) 226 tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr 227 t2Bcc %bb.9, 0 /* CC::eq */, killed $cpsr 228 229 bb.5.while.body: 230 successors: %bb.4(0x7c000000) 231 liveins: $r0, $r1 232 233 renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.next4) 234 tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 235 t2IT 0, 4, implicit-def $itstate 236 renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate 237 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate 238 t2B %bb.4, 14 /* CC::al */, $noreg 239 240 bb.9.return: 241 liveins: $r0 242 243 tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0 244 245 bb.1.while.cond9.preheader: 246 successors: %bb.7(0x50000000) 247 liveins: $r0, $r1 248 249 tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 250 t2IT 0, 4, implicit-def $itstate 251 renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate 252 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate 253 t2B %bb.7, 14 /* CC::al */, $noreg 254 255 bb.7.land.rhs11.lr.ph: 256 successors: %bb.8(0x80000000) 257 liveins: $r0, $r1 258 259 renamable $r1 = t2LDRSHi12 killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (load (s16) from %ir.data16143) 260 261 bb.8.land.rhs11: 262 successors: %bb.6(0x80000000) 263 liveins: $r0, $r1 264 265 renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.info12) 266 renamable $r2 = tLDRBi killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (load (s8) from %ir.data166, align 2) 267 tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr 268 t2IT 0, 8, implicit-def $itstate 269 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate 270 t2B %bb.6, 14 /* CC::al */, $noreg 271 272 bb.6.while.body19: 273 successors: %bb.8(0x7c000000) 274 liveins: $r0, $r1 275 276 renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.next205) 277 tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 278 t2IT 0, 4, implicit-def $itstate 279 renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate 280 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate 281 t2B %bb.8, 14 /* CC::al */, $noreg 282 283... 284