1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -mtriple=armv8.1m.main -mattr=+mve -S -mve-tail-predication -tail-predication=enabled %s -o - | FileCheck %s 3 4define void @mat_vec_sext_i16(ptr nocapture readonly %A, ptr nocapture readonly %B, ptr noalias nocapture %C, i32 %N) { 5; CHECK-LABEL: @mat_vec_sext_i16( 6; CHECK-NEXT: entry: 7; CHECK-NEXT: [[CMP24:%.*]] = icmp eq i32 [[N:%.*]], 0 8; CHECK-NEXT: br i1 [[CMP24]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER_US_PREHEADER:%.*]] 9; CHECK: for.cond1.preheader.us.preheader: 10; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 3 11; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -4 12; CHECK-NEXT: [[TT:%.*]] = add i32 [[N_VEC]], -4 13; CHECK-NEXT: [[TT1:%.*]] = lshr i32 [[TT]], 2 14; CHECK-NEXT: [[TT2:%.*]] = add nuw nsw i32 [[TT1]], 1 15; CHECK-NEXT: br label [[FOR_COND1_PREHEADER_US:%.*]] 16; CHECK: for.cond1.preheader.us: 17; CHECK-NEXT: [[I_025_US:%.*]] = phi i32 [ [[INC10_US:%.*]], [[MIDDLE_BLOCK:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ] 18; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds ptr, ptr [[A:%.*]], i32 [[I_025_US]] 19; CHECK-NEXT: [[TT3:%.*]] = load ptr, ptr [[ARRAYIDX_US]], align 4 20; CHECK-NEXT: [[ARRAYIDX8_US:%.*]] = getelementptr inbounds i32, ptr [[C:%.*]], i32 [[I_025_US]] 21; CHECK-NEXT: [[ARRAYIDX8_PROMOTED_US:%.*]] = load i32, ptr [[ARRAYIDX8_US]], align 4 22; CHECK-NEXT: [[TT4:%.*]] = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 [[ARRAYIDX8_PROMOTED_US]], i32 0 23; CHECK-NEXT: [[START:%.*]] = call i32 @llvm.start.loop.iterations.i32(i32 [[TT2]]) 24; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 25; CHECK: vector.body: 26; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[FOR_COND1_PREHEADER_US]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 27; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ [[TT4]], [[FOR_COND1_PREHEADER_US]] ], [ [[TT14:%.*]], [[VECTOR_BODY]] ] 28; CHECK-NEXT: [[TT5:%.*]] = phi i32 [ [[START]], [[FOR_COND1_PREHEADER_US]] ], [ [[TT15:%.*]], [[VECTOR_BODY]] ] 29; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[N]], [[FOR_COND1_PREHEADER_US]] ], [ [[TMP2:%.*]], [[VECTOR_BODY]] ] 30; CHECK-NEXT: [[TT6:%.*]] = getelementptr inbounds i16, ptr [[TT3]], i32 [[INDEX]] 31; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 [[TMP0]]) 32; CHECK-NEXT: [[TMP2]] = sub i32 [[TMP0]], 4 33; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr [[TT6]], i32 2, <4 x i1> [[TMP1]], <4 x i16> undef) 34; CHECK-NEXT: [[TT9:%.*]] = sext <4 x i16> [[WIDE_MASKED_LOAD]] to <4 x i32> 35; CHECK-NEXT: [[TT10:%.*]] = getelementptr inbounds i16, ptr [[B:%.*]], i32 [[INDEX]] 36; CHECK-NEXT: [[WIDE_MASKED_LOAD30:%.*]] = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr [[TT10]], i32 2, <4 x i1> [[TMP1]], <4 x i16> undef) 37; CHECK-NEXT: [[TT12:%.*]] = sext <4 x i16> [[WIDE_MASKED_LOAD30]] to <4 x i32> 38; CHECK-NEXT: [[TT13:%.*]] = mul nsw <4 x i32> [[TT12]], [[TT9]] 39; CHECK-NEXT: [[TT14]] = add nsw <4 x i32> [[TT13]], [[VEC_PHI]] 40; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4 41; CHECK-NEXT: [[TT15]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TT5]], i32 1) 42; CHECK-NEXT: [[TT16:%.*]] = icmp ne i32 [[TT15]], 0 43; CHECK-NEXT: br i1 [[TT16]], label [[VECTOR_BODY]], label [[MIDDLE_BLOCK]] 44; CHECK: middle.block: 45; CHECK-NEXT: [[TT17:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[TT14]], <4 x i32> [[VEC_PHI]] 46; CHECK-NEXT: [[TT18:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TT17]]) 47; CHECK-NEXT: store i32 [[TT18]], ptr [[ARRAYIDX8_US]], align 4 48; CHECK-NEXT: [[INC10_US]] = add nuw i32 [[I_025_US]], 1 49; CHECK-NEXT: [[EXITCOND27:%.*]] = icmp eq i32 [[INC10_US]], [[N]] 50; CHECK-NEXT: br i1 [[EXITCOND27]], label [[FOR_COND_CLEANUP]], label [[FOR_COND1_PREHEADER_US]] 51; CHECK: for.cond.cleanup: 52; CHECK-NEXT: ret void 53; 54entry: 55 %cmp24 = icmp eq i32 %N, 0 56 br i1 %cmp24, label %for.cond.cleanup, label %for.cond1.preheader.us.preheader 57 58for.cond1.preheader.us.preheader: ; preds = %entry 59 %n.rnd.up = add i32 %N, 3 60 %n.vec = and i32 %n.rnd.up, -4 61 %tt = add i32 %n.vec, -4 62 %tt1 = lshr i32 %tt, 2 63 %tt2 = add nuw nsw i32 %tt1, 1 64 br label %for.cond1.preheader.us 65 66for.cond1.preheader.us: ; preds = %middle.block, %for.cond1.preheader.us.preheader 67 %i.025.us = phi i32 [ %inc10.us, %middle.block ], [ 0, %for.cond1.preheader.us.preheader ] 68 %arrayidx.us = getelementptr inbounds ptr, ptr %A, i32 %i.025.us 69 %tt3 = load ptr, ptr %arrayidx.us, align 4 70 %arrayidx8.us = getelementptr inbounds i32, ptr %C, i32 %i.025.us 71 %arrayidx8.promoted.us = load i32, ptr %arrayidx8.us, align 4 72 %tt4 = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 %arrayidx8.promoted.us, i32 0 73 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tt2) 74 br label %vector.body 75 76vector.body: ; preds = %vector.body, %for.cond1.preheader.us 77 %index = phi i32 [ 0, %for.cond1.preheader.us ], [ %index.next, %vector.body ] 78 %vec.phi = phi <4 x i32> [ %tt4, %for.cond1.preheader.us ], [ %tt14, %vector.body ] 79 %tt5 = phi i32 [ %start, %for.cond1.preheader.us ], [ %tt15, %vector.body ] 80 %tt6 = getelementptr inbounds i16, ptr %tt3, i32 %index 81 %tt7 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N) 82 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %tt6, i32 2, <4 x i1> %tt7, <4 x i16> undef) 83 %tt9 = sext <4 x i16> %wide.masked.load to <4 x i32> 84 %tt10 = getelementptr inbounds i16, ptr %B, i32 %index 85 %wide.masked.load30 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %tt10, i32 2, <4 x i1> %tt7, <4 x i16> undef) 86 %tt12 = sext <4 x i16> %wide.masked.load30 to <4 x i32> 87 %tt13 = mul nsw <4 x i32> %tt12, %tt9 88 %tt14 = add nsw <4 x i32> %tt13, %vec.phi 89 %index.next = add i32 %index, 4 90 %tt15 = call i32 @llvm.loop.decrement.reg.i32(i32 %tt5, i32 1) 91 %tt16 = icmp ne i32 %tt15, 0 92 br i1 %tt16, label %vector.body, label %middle.block 93 94middle.block: ; preds = %vector.body 95 %tt17 = select <4 x i1> %tt7, <4 x i32> %tt14, <4 x i32> %vec.phi 96 %tt18 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tt17) 97 store i32 %tt18, ptr %arrayidx8.us, align 4 98 %inc10.us = add nuw i32 %i.025.us, 1 99 %exitcond27 = icmp eq i32 %inc10.us, %N 100 br i1 %exitcond27, label %for.cond.cleanup, label %for.cond1.preheader.us 101 102for.cond.cleanup: ; preds = %middle.block, %entry 103 ret void 104} 105 106define void @mat_vec_i32(ptr nocapture readonly %A, ptr nocapture readonly %B, ptr noalias nocapture %C, i32 %N) { 107; CHECK-LABEL: @mat_vec_i32( 108; CHECK-NEXT: entry: 109; CHECK-NEXT: [[CMP23:%.*]] = icmp eq i32 [[N:%.*]], 0 110; CHECK-NEXT: br i1 [[CMP23]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER_US_PREHEADER:%.*]] 111; CHECK: for.cond1.preheader.us.preheader: 112; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N]], 3 113; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -4 114; CHECK-NEXT: [[TT:%.*]] = add i32 [[N_VEC]], -4 115; CHECK-NEXT: [[TT1:%.*]] = lshr i32 [[TT]], 2 116; CHECK-NEXT: [[TT2:%.*]] = add nuw nsw i32 [[TT1]], 1 117; CHECK-NEXT: br label [[FOR_COND1_PREHEADER_US:%.*]] 118; CHECK: for.cond1.preheader.us: 119; CHECK-NEXT: [[I_024_US:%.*]] = phi i32 [ [[INC9_US:%.*]], [[MIDDLE_BLOCK:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ] 120; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds ptr, ptr [[A:%.*]], i32 [[I_024_US]] 121; CHECK-NEXT: [[TT3:%.*]] = load ptr, ptr [[ARRAYIDX_US]], align 4 122; CHECK-NEXT: [[ARRAYIDX7_US:%.*]] = getelementptr inbounds i32, ptr [[C:%.*]], i32 [[I_024_US]] 123; CHECK-NEXT: [[ARRAYIDX7_PROMOTED_US:%.*]] = load i32, ptr [[ARRAYIDX7_US]], align 4 124; CHECK-NEXT: [[TT4:%.*]] = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 [[ARRAYIDX7_PROMOTED_US]], i32 0 125; CHECK-NEXT: [[START:%.*]] = call i32 @llvm.start.loop.iterations.i32(i32 [[TT2]]) 126; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 127; CHECK: vector.body: 128; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[FOR_COND1_PREHEADER_US]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 129; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ [[TT4]], [[FOR_COND1_PREHEADER_US]] ], [ [[TT12:%.*]], [[VECTOR_BODY]] ] 130; CHECK-NEXT: [[TT5:%.*]] = phi i32 [ [[START]], [[FOR_COND1_PREHEADER_US]] ], [ [[TT13:%.*]], [[VECTOR_BODY]] ] 131; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[N]], [[FOR_COND1_PREHEADER_US]] ], [ [[TMP2:%.*]], [[VECTOR_BODY]] ] 132; CHECK-NEXT: [[TT6:%.*]] = getelementptr inbounds i32, ptr [[TT3]], i32 [[INDEX]] 133; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 [[TMP0]]) 134; CHECK-NEXT: [[TMP2]] = sub i32 [[TMP0]], 4 135; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TT6]], i32 4, <4 x i1> [[TMP1]], <4 x i32> undef) 136; CHECK-NEXT: [[TT9:%.*]] = getelementptr inbounds i32, ptr [[B:%.*]], i32 [[INDEX]] 137; CHECK-NEXT: [[WIDE_MASKED_LOAD29:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TT9]], i32 4, <4 x i1> [[TMP1]], <4 x i32> undef) 138; CHECK-NEXT: [[TT11:%.*]] = mul nsw <4 x i32> [[WIDE_MASKED_LOAD29]], [[WIDE_MASKED_LOAD]] 139; CHECK-NEXT: [[TT12]] = add nsw <4 x i32> [[VEC_PHI]], [[TT11]] 140; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4 141; CHECK-NEXT: [[TT13]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TT5]], i32 1) 142; CHECK-NEXT: [[TT14:%.*]] = icmp ne i32 [[TT13]], 0 143; CHECK-NEXT: br i1 [[TT14]], label [[VECTOR_BODY]], label [[MIDDLE_BLOCK]] 144; CHECK: middle.block: 145; CHECK-NEXT: [[TT15:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[TT12]], <4 x i32> [[VEC_PHI]] 146; CHECK-NEXT: [[TT16:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TT15]]) 147; CHECK-NEXT: store i32 [[TT16]], ptr [[ARRAYIDX7_US]], align 4 148; CHECK-NEXT: [[INC9_US]] = add nuw i32 [[I_024_US]], 1 149; CHECK-NEXT: [[EXITCOND26:%.*]] = icmp eq i32 [[INC9_US]], [[N]] 150; CHECK-NEXT: br i1 [[EXITCOND26]], label [[FOR_COND_CLEANUP]], label [[FOR_COND1_PREHEADER_US]] 151; CHECK: for.cond.cleanup: 152; CHECK-NEXT: ret void 153; 154entry: 155 %cmp23 = icmp eq i32 %N, 0 156 br i1 %cmp23, label %for.cond.cleanup, label %for.cond1.preheader.us.preheader 157 158for.cond1.preheader.us.preheader: ; preds = %entry 159 %n.rnd.up = add i32 %N, 3 160 %n.vec = and i32 %n.rnd.up, -4 161 %tt = add i32 %n.vec, -4 162 %tt1 = lshr i32 %tt, 2 163 %tt2 = add nuw nsw i32 %tt1, 1 164 br label %for.cond1.preheader.us 165 166for.cond1.preheader.us: ; preds = %middle.block, %for.cond1.preheader.us.preheader 167 %i.024.us = phi i32 [ %inc9.us, %middle.block ], [ 0, %for.cond1.preheader.us.preheader ] 168 %arrayidx.us = getelementptr inbounds ptr, ptr %A, i32 %i.024.us 169 %tt3 = load ptr, ptr %arrayidx.us, align 4 170 %arrayidx7.us = getelementptr inbounds i32, ptr %C, i32 %i.024.us 171 %arrayidx7.promoted.us = load i32, ptr %arrayidx7.us, align 4 172 %tt4 = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 %arrayidx7.promoted.us, i32 0 173 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tt2) 174 br label %vector.body 175 176vector.body: ; preds = %vector.body, %for.cond1.preheader.us 177 %index = phi i32 [ 0, %for.cond1.preheader.us ], [ %index.next, %vector.body ] 178 %vec.phi = phi <4 x i32> [ %tt4, %for.cond1.preheader.us ], [ %tt12, %vector.body ] 179 %tt5 = phi i32 [ %start, %for.cond1.preheader.us ], [ %tt13, %vector.body ] 180 %tt6 = getelementptr inbounds i32, ptr %tt3, i32 %index 181 %tt7 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N) 182 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %tt6, i32 4, <4 x i1> %tt7, <4 x i32> undef) 183 %tt9 = getelementptr inbounds i32, ptr %B, i32 %index 184 %wide.masked.load29 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %tt9, i32 4, <4 x i1> %tt7, <4 x i32> undef) 185 %tt11 = mul nsw <4 x i32> %wide.masked.load29, %wide.masked.load 186 %tt12 = add nsw <4 x i32> %vec.phi, %tt11 187 %index.next = add i32 %index, 4 188 %tt13 = call i32 @llvm.loop.decrement.reg.i32(i32 %tt5, i32 1) 189 %tt14 = icmp ne i32 %tt13, 0 190 br i1 %tt14, label %vector.body, label %middle.block 191 192middle.block: ; preds = %vector.body 193 %tt15 = select <4 x i1> %tt7, <4 x i32> %tt12, <4 x i32> %vec.phi 194 %tt16 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tt15) 195 store i32 %tt16, ptr %arrayidx7.us, align 4 196 %inc9.us = add nuw i32 %i.024.us, 1 197 %exitcond26 = icmp eq i32 %inc9.us, %N 198 br i1 %exitcond26, label %for.cond.cleanup, label %for.cond1.preheader.us 199 200for.cond.cleanup: ; preds = %middle.block, %entry 201 ret void 202} 203 204 205; Function Attrs: argmemonly nounwind readonly willreturn 206declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) #0 207 208; Function Attrs: argmemonly nounwind readonly willreturn 209declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>) #0 210 211; Function Attrs: nounwind readnone willreturn 212declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #1 213 214; Function Attrs: noduplicate nounwind 215declare i32 @llvm.start.loop.iterations.i32(i32) #2 216 217; Function Attrs: noduplicate nounwind 218declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #2 219 220declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) 221 222attributes #0 = { argmemonly nounwind readonly willreturn } 223attributes #1 = { nounwind readnone willreturn } 224attributes #2 = { noduplicate nounwind } 225