1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=armv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 define void @size_limit(ptr nocapture %a, ptr nocapture readonly %b, ptr nocapture readonly %c, i32 %N) { 6 entry: 7 %cmp8 = icmp eq i32 %N, 0 8 br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader 9 10 for.body.preheader: ; preds = %entry 11 %start = call i32 @llvm.start.loop.iterations.i32(i32 %N) 12 br label %for.body 13 14 for.cond.cleanup: ; preds = %for.end, %entry 15 ret void 16 17 for.body: ; preds = %for.end, %for.body.preheader 18 %lsr.iv4 = phi ptr [ %b, %for.body.preheader ], [ %scevgep5, %for.end ] 19 %lsr.iv2 = phi ptr [ %c, %for.body.preheader ], [ %scevgep3, %for.end ] 20 %lsr.iv1 = phi ptr [ %a, %for.body.preheader ], [ %scevgep, %for.end ] 21 %lsr.iv = phi i32 [ %start, %for.body.preheader ], [ %lsr.iv.next, %for.end ] 22 %size = call i32 @llvm.arm.space(i32 3072, i32 undef) 23 %0 = load i32, ptr %lsr.iv4, align 4 24 %1 = load i32, ptr %lsr.iv2, align 4 25 %mul = mul nsw i32 %1, %0 26 store i32 %mul, ptr %lsr.iv1, align 4 27 %cmp = icmp ne i32 %0, 0 28 br i1 %cmp, label %middle.block, label %for.end 29 30 middle.block: ; preds = %for.body 31 %div = udiv i32 %1, %0 32 store i32 %div, ptr %lsr.iv1, align 4 33 %size.1 = call i32 @llvm.arm.space(i32 1024, i32 undef) 34 br label %for.end 35 36 for.end: ; preds = %middle.block, %for.body 37 %scevgep = getelementptr i32, ptr %lsr.iv1, i32 1 38 %scevgep3 = getelementptr i32, ptr %lsr.iv2, i32 1 39 %scevgep5 = getelementptr i32, ptr %lsr.iv4, i32 1 40 %lsr.iv.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1) 41 %exitcond = icmp eq i32 %lsr.iv.next, 0 42 br i1 %exitcond, label %for.cond.cleanup, label %for.body 43 } 44 45 declare i32 @llvm.arm.space(i32 immarg, i32) #0 46 47 declare i32 @llvm.start.loop.iterations.i32(i32) #1 48 49 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 50 51 declare void @llvm.stackprotector(ptr, ptr) #0 52 53 attributes #0 = { nounwind } 54 attributes #1 = { noduplicate nounwind } 55 56... 57--- 58name: size_limit 59alignment: 2 60exposesReturnsTwice: false 61legalized: false 62regBankSelected: false 63selected: false 64failedISel: false 65tracksRegLiveness: true 66hasWinCFI: false 67registers: [] 68liveins: 69 - { reg: '$r0', virtual-reg: '' } 70 - { reg: '$r1', virtual-reg: '' } 71 - { reg: '$r2', virtual-reg: '' } 72 - { reg: '$r3', virtual-reg: '' } 73frameInfo: 74 isFrameAddressTaken: false 75 isReturnAddressTaken: false 76 hasStackMap: false 77 hasPatchPoint: false 78 stackSize: 8 79 offsetAdjustment: 0 80 maxAlignment: 4 81 adjustsStack: false 82 hasCalls: false 83 stackProtector: '' 84 maxCallFrameSize: 0 85 cvBytesOfCalleeSavedRegisters: 0 86 hasOpaqueSPAdjustment: false 87 hasVAStart: false 88 hasMustTailInVarArgFunc: false 89 localFrameSize: 0 90 savePoint: '' 91 restorePoint: '' 92fixedStack: [] 93stack: 94 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 95 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 96 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 97 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 98 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 99 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 100callSites: [] 101constants: [] 102machineFunctionInfo: {} 103body: | 104 ; CHECK-LABEL: name: size_limit 105 ; CHECK: bb.0.entry: 106 ; CHECK-NEXT: successors: %bb.1(0x80000000) 107 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 108 ; CHECK-NEXT: {{ $}} 109 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 110 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 111 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 112 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 113 ; CHECK-NEXT: tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 114 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 115 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 116 ; CHECK-NEXT: {{ $}} 117 ; CHECK-NEXT: bb.1.for.body.preheader: 118 ; CHECK-NEXT: successors: %bb.2(0x80000000) 119 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 120 ; CHECK-NEXT: {{ $}} 121 ; CHECK-NEXT: dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg 122 ; CHECK-NEXT: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg 123 ; CHECK-NEXT: tB %bb.2, 14 /* CC::al */, $noreg 124 ; CHECK-NEXT: {{ $}} 125 ; CHECK-NEXT: bb.2.for.end: 126 ; CHECK-NEXT: successors: %bb.5(0x04000000), %bb.3(0x7c000000) 127 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 128 ; CHECK-NEXT: {{ $}} 129 ; CHECK-NEXT: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 130 ; CHECK-NEXT: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 131 ; CHECK-NEXT: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg 132 ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr 133 ; CHECK-NEXT: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr 134 ; CHECK-NEXT: t2B %bb.5, 14 /* CC::al */, $noreg 135 ; CHECK-NEXT: {{ $}} 136 ; CHECK-NEXT: bb.3.for.body: 137 ; CHECK-NEXT: successors: %bb.4(0x50000000), %bb.2(0x30000000) 138 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2 139 ; CHECK-NEXT: {{ $}} 140 ; CHECK-NEXT: dead renamable $r3 = SPACE 3072, undef renamable $r0 141 ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r1, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv4) 142 ; CHECK-NEXT: renamable $r12 = t2LDRi12 renamable $r2, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv2) 143 ; CHECK-NEXT: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 144 ; CHECK-NEXT: renamable $r4 = nsw t2MUL renamable $r12, renamable $r3, 14 /* CC::al */, $noreg 145 ; CHECK-NEXT: tSTRi killed renamable $r4, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.lsr.iv1) 146 ; CHECK-NEXT: t2Bcc %bb.2, 0 /* CC::eq */, killed $cpsr 147 ; CHECK-NEXT: {{ $}} 148 ; CHECK-NEXT: bb.4.middle.block: 149 ; CHECK-NEXT: successors: %bb.2(0x80000000) 150 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r12 151 ; CHECK-NEXT: {{ $}} 152 ; CHECK-NEXT: renamable $r3 = t2UDIV killed renamable $r12, killed renamable $r3, 14 /* CC::al */, $noreg 153 ; CHECK-NEXT: tSTRi killed renamable $r3, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.lsr.iv1) 154 ; CHECK-NEXT: dead renamable $r3 = SPACE 1024, undef renamable $r0 155 ; CHECK-NEXT: t2B %bb.2, 14 /* CC::al */, $noreg 156 ; CHECK-NEXT: {{ $}} 157 ; CHECK-NEXT: bb.5.for.cond.cleanup: 158 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 159 bb.0.entry: 160 successors: %bb.1(0x80000000) 161 liveins: $r0, $r1, $r2, $r3, $r4, $lr 162 163 frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 164 frame-setup CFI_INSTRUCTION def_cfa_offset 8 165 frame-setup CFI_INSTRUCTION offset $lr, -4 166 frame-setup CFI_INSTRUCTION offset $r4, -8 167 tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr 168 t2IT 0, 8, implicit-def $itstate 169 tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate 170 171 bb.1.for.body.preheader: 172 successors: %bb.2(0x80000000) 173 liveins: $r0, $r1, $r2, $r3, $r4, $lr 174 175 $lr = tMOVr $r3, 14, $noreg 176 $lr = t2DoLoopStart killed $r3 177 tB %bb.2, 14, $noreg 178 179 bb.2.for.end: 180 successors: %bb.5(0x04000000), %bb.3(0x7c000000) 181 liveins: $lr, $r0, $r1, $r2 182 183 renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg 184 renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14, $noreg 185 renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg 186 renamable $lr = t2LoopDec killed renamable $lr, 1 187 t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr 188 t2B %bb.5, 14, $noreg 189 190 bb.3.for.body: 191 successors: %bb.4(0x50000000), %bb.2(0x30000000) 192 liveins: $lr, $r0, $r1, $r2 193 194 dead renamable $r3 = SPACE 3072, undef renamable $r0 195 renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (load (s32) from %ir.lsr.iv4) 196 renamable $r12 = t2LDRi12 renamable $r2, 0, 14, $noreg :: (load (s32) from %ir.lsr.iv2) 197 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr 198 renamable $r4 = nsw t2MUL renamable $r12, renamable $r3, 14, $noreg 199 tSTRi killed renamable $r4, renamable $r0, 0, 14, $noreg :: (store (s32) into %ir.lsr.iv1) 200 t2Bcc %bb.2, 0, killed $cpsr 201 202 bb.4.middle.block: 203 successors: %bb.2(0x80000000) 204 liveins: $lr, $r0, $r1, $r2, $r3, $r12 205 206 renamable $r3 = t2UDIV killed renamable $r12, killed renamable $r3, 14, $noreg 207 tSTRi killed renamable $r3, renamable $r0, 0, 14, $noreg :: (store (s32) into %ir.lsr.iv1) 208 dead renamable $r3 = SPACE 1024, undef renamable $r0 209 t2B %bb.2, 14, $noreg 210 211 bb.5.for.cond.cleanup: 212 tPOP_RET 14, $noreg, def $r4, def $pc 213 214... 215