1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs -tail-predication=enabled -o - %s | FileCheck %s 3 4define arm_aapcs_vfpcc void @arm_var_f32_mve(ptr %pSrc, i32 %blockSize, ptr nocapture %pResult) { 5; CHECK-LABEL: arm_var_f32_mve: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: .save {r7, lr} 8; CHECK-NEXT: push {r7, lr} 9; CHECK-NEXT: vmov.i32 q0, #0x0 10; CHECK-NEXT: mov r12, r0 11; CHECK-NEXT: dlstp.32 lr, r1 12; CHECK-NEXT: .LBB0_1: @ %do.body.i 13; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 14; CHECK-NEXT: vldrw.u32 q1, [r12], #16 15; CHECK-NEXT: vadd.f32 q0, q0, q1 16; CHECK-NEXT: letp lr, .LBB0_1 17; CHECK-NEXT: @ %bb.2: @ %arm_mean_f32_mve.exit 18; CHECK-NEXT: vmov s0, r1 19; CHECK-NEXT: vadd.f32 s2, s3, s3 20; CHECK-NEXT: vcvt.f32.u32 s0, s0 21; CHECK-NEXT: vdiv.f32 s0, s2, s0 22; CHECK-NEXT: vmov r12, s0 23; CHECK-NEXT: vmov.i32 q0, #0x0 24; CHECK-NEXT: dlstp.32 lr, r1 25; CHECK-NEXT: .LBB0_3: @ %do.body 26; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 27; CHECK-NEXT: vldrw.u32 q1, [r0], #16 28; CHECK-NEXT: vsub.f32 q1, q1, r12 29; CHECK-NEXT: vfma.f32 q0, q1, q1 30; CHECK-NEXT: letp lr, .LBB0_3 31; CHECK-NEXT: @ %bb.4: @ %do.end 32; CHECK-NEXT: subs r0, r1, #1 33; CHECK-NEXT: vadd.f32 s0, s3, s3 34; CHECK-NEXT: vmov s2, r0 35; CHECK-NEXT: vcvt.f32.u32 s2, s2 36; CHECK-NEXT: vdiv.f32 s0, s0, s2 37; CHECK-NEXT: vstr s0, [r2] 38; CHECK-NEXT: pop {r7, pc} 39entry: 40 br label %do.body.i 41 42do.body.i: ; preds = %entry, %do.body.i 43 %blkCnt.0.i = phi i32 [ %sub.i, %do.body.i ], [ %blockSize, %entry ] 44 %sumVec.0.i = phi <4 x float> [ %3, %do.body.i ], [ zeroinitializer, %entry ] 45 %pSrc.addr.0.i = phi ptr [ %add.ptr.i, %do.body.i ], [ %pSrc, %entry ] 46 %0 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0.i) 47 %1 = bitcast ptr %pSrc.addr.0.i to ptr 48 %2 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr %1, i32 4, <4 x i1> %0, <4 x float> zeroinitializer) 49 %3 = tail call fast <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %sumVec.0.i, <4 x float> %2, <4 x i1> %0, <4 x float> %sumVec.0.i) 50 %sub.i = add nsw i32 %blkCnt.0.i, -4 51 %add.ptr.i = getelementptr inbounds float, ptr %pSrc.addr.0.i, i32 4 52 %cmp.i = icmp sgt i32 %blkCnt.0.i, 4 53 br i1 %cmp.i, label %do.body.i, label %arm_mean_f32_mve.exit 54 55arm_mean_f32_mve.exit: ; preds = %do.body.i 56 %4 = extractelement <4 x float> %3, i32 3 57 %add2.i.i = fadd fast float %4, %4 58 %conv.i = uitofp i32 %blockSize to float 59 %div.i = fdiv fast float %add2.i.i, %conv.i 60 %.splatinsert = insertelement <4 x float> undef, float %div.i, i32 0 61 %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer 62 br label %do.body 63 64do.body: ; preds = %do.body, %arm_mean_f32_mve.exit 65 %blkCnt.0 = phi i32 [ %blockSize, %arm_mean_f32_mve.exit ], [ %sub, %do.body ] 66 %sumVec.0 = phi <4 x float> [ zeroinitializer, %arm_mean_f32_mve.exit ], [ %9, %do.body ] 67 %pSrc.addr.0 = phi ptr [ %pSrc, %arm_mean_f32_mve.exit ], [ %add.ptr, %do.body ] 68 %5 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0) 69 %6 = bitcast ptr %pSrc.addr.0 to ptr 70 %7 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr %6, i32 4, <4 x i1> %5, <4 x float> zeroinitializer) 71 %8 = tail call fast <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %7, <4 x float> %.splat, <4 x i1> %5, <4 x float> undef) 72 %9 = tail call fast <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float> %8, <4 x float> %8, <4 x float> %sumVec.0, <4 x i1> %5) 73 %sub = add nsw i32 %blkCnt.0, -4 74 %add.ptr = getelementptr inbounds float, ptr %pSrc.addr.0, i32 4 75 %cmp1 = icmp sgt i32 %blkCnt.0, 4 76 br i1 %cmp1, label %do.body, label %do.end 77 78do.end: ; preds = %do.body 79 %10 = extractelement <4 x float> %9, i32 3 80 %add2.i = fadd fast float %10, %10 81 %sub2 = add i32 %blockSize, -1 82 %conv = uitofp i32 %sub2 to float 83 %div = fdiv fast float %add2.i, %conv 84 br label %cleanup 85 86cleanup: ; preds = %entry, %do.end 87 store float %div, ptr %pResult, align 4 88 ret void 89} 90 91declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) 92 93declare <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x float>, <4 x i1>) 94 95declare <4 x i1> @llvm.arm.mve.vctp32(i32) 96 97declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>) 98 99declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) 100 101