1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3--- | 4 define dso_local arm_aapcs_vfpcc void @start_before_elems(ptr noalias nocapture %a, ptr nocapture readonly %b, ptr nocapture readonly %c, i32 %N) local_unnamed_addr #0 { 5 entry: 6 %div = lshr i32 %N, 1 7 %cmp9 = icmp eq i32 %div, 0 8 %0 = add nuw i32 %div, 3 9 %1 = lshr i32 %0, 2 10 %2 = shl nuw i32 %1, 2 11 %3 = add i32 %2, -4 12 %4 = lshr i32 %3, 2 13 %5 = add nuw nsw i32 %4, 1 14 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph 15 16 vector.ph: ; preds = %entry 17 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 18 br label %vector.body 19 20 vector.body: ; preds = %vector.body, %vector.ph 21 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 22 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] 23 %6 = phi i32 [ %start, %vector.ph ], [ %13, %vector.body ] 24 %7 = phi i32 [ %div, %vector.ph ], [ %9, %vector.body ] 25 %lsr.iv1 = bitcast ptr %lsr.iv to ptr 26 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7) 27 %9 = sub i32 %7, 4 28 %scevgep4 = getelementptr i8, ptr %b, i32 %index 29 %scevgep45 = bitcast ptr %scevgep4 to ptr 30 %wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %scevgep45, i32 1, <4 x i1> %8, <4 x i8> undef) 31 %10 = zext <4 x i8> %wide.masked.load to <4 x i32> 32 %scevgep2 = getelementptr i8, ptr %c, i32 %index 33 %scevgep23 = bitcast ptr %scevgep2 to ptr 34 %wide.masked.load13 = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr %scevgep23, i32 1, <4 x i1> %8, <4 x i8> undef) 35 %11 = zext <4 x i8> %wide.masked.load13 to <4 x i32> 36 %12 = mul nuw nsw <4 x i32> %11, %10 37 call void @llvm.masked.store.v4i32.p0(<4 x i32> %12, ptr %lsr.iv1, i32 4, <4 x i1> %8) 38 %index.next = add i32 %index, 4 39 %scevgep = getelementptr i32, ptr %lsr.iv, i32 4 40 %13 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 41 %14 = icmp ne i32 %13, 0 42 br i1 %14, label %vector.body, label %for.cond.cleanup 43 44 for.cond.cleanup: ; preds = %vector.body, %entry 45 ret void 46 } 47 declare <4 x i8> @llvm.masked.load.v4i8.p0(ptr, i32 immarg, <4 x i1>, <4 x i8>) 48 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) 49 declare i32 @llvm.start.loop.iterations.i32(i32) 50 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 51 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 52... 53--- 54name: start_before_elems 55alignment: 2 56exposesReturnsTwice: false 57legalized: false 58regBankSelected: false 59selected: false 60failedISel: false 61tracksRegLiveness: true 62hasWinCFI: false 63registers: [] 64liveins: 65 - { reg: '$r0', virtual-reg: '' } 66 - { reg: '$r1', virtual-reg: '' } 67 - { reg: '$r2', virtual-reg: '' } 68 - { reg: '$r3', virtual-reg: '' } 69frameInfo: 70 isFrameAddressTaken: false 71 isReturnAddressTaken: false 72 hasStackMap: false 73 hasPatchPoint: false 74 stackSize: 8 75 offsetAdjustment: 0 76 maxAlignment: 4 77 adjustsStack: false 78 hasCalls: false 79 stackProtector: '' 80 maxCallFrameSize: 0 81 cvBytesOfCalleeSavedRegisters: 0 82 hasOpaqueSPAdjustment: false 83 hasVAStart: false 84 hasMustTailInVarArgFunc: false 85 localFrameSize: 0 86 savePoint: '' 87 restorePoint: '' 88fixedStack: [] 89stack: 90 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 91 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 92 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 93 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 94 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 95 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 96callSites: [] 97constants: [] 98machineFunctionInfo: {} 99body: | 100 ; CHECK-LABEL: name: start_before_elems 101 ; CHECK: bb.0.entry: 102 ; CHECK-NEXT: successors: %bb.1(0x80000000) 103 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r4 104 ; CHECK-NEXT: {{ $}} 105 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 106 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 107 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 108 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 109 ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 110 ; CHECK-NEXT: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr 111 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 112 ; CHECK-NEXT: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate 113 ; CHECK-NEXT: {{ $}} 114 ; CHECK-NEXT: bb.1.vector.ph: 115 ; CHECK-NEXT: successors: %bb.2(0x80000000) 116 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 117 ; CHECK-NEXT: {{ $}} 118 ; CHECK-NEXT: renamable $r12 = t2LSRri killed renamable $r3, 1, 14 /* CC::al */, $noreg, $noreg 119 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 120 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r12 121 ; CHECK-NEXT: {{ $}} 122 ; CHECK-NEXT: bb.2.vector.body: 123 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 124 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 125 ; CHECK-NEXT: {{ $}} 126 ; CHECK-NEXT: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg 127 ; CHECK-NEXT: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s32) from %ir.scevgep45, align 1) 128 ; CHECK-NEXT: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg 129 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg 130 ; CHECK-NEXT: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s32) from %ir.scevgep23, align 1) 131 ; CHECK-NEXT: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 132 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) 133 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 134 ; CHECK-NEXT: {{ $}} 135 ; CHECK-NEXT: bb.3.for.cond.cleanup: 136 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 137 bb.0.entry: 138 successors: %bb.1(0x80000000) 139 liveins: $r0, $r1, $r2, $r3, $r4, $lr 140 141 frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 142 frame-setup CFI_INSTRUCTION def_cfa_offset 8 143 frame-setup CFI_INSTRUCTION offset $lr, -4 144 frame-setup CFI_INSTRUCTION offset $r4, -8 145 renamable $r12 = t2MOVi 0, 14, $noreg, $noreg 146 t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr 147 t2IT 0, 8, implicit-def $itstate 148 tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate 149 150 bb.1.vector.ph: 151 successors: %bb.2(0x80000000) 152 liveins: $r0, $r1, $r2, $r3, $r4, $lr 153 154 renamable $r12 = t2MOVi 3, 14, $noreg, $noreg 155 renamable $lr = t2MOVi 1, 14, $noreg, $noreg 156 renamable $r12 = nuw t2ADDrs killed renamable $r12, renamable $r3, 11, 14, $noreg, $noreg 157 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg 158 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 159 renamable $r5 = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg 160 renamable $r12 = t2LSRri killed renamable $r3, 1, 14, $noreg, $noreg 161 renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg 162 $lr = t2DoLoopStart renamable $r5 163 $lr = tMOVr killed $r5, 14, $noreg 164 165 bb.2.vector.body: 166 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 167 liveins: $lr, $r0, $r1, $r2, $r3, $r12 168 169 renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg 170 renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg 171 MVE_VPST 8, implicit $vpr 172 renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep45, align 1) 173 renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg 174 renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg 175 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 176 MVE_VPST 8, implicit $vpr 177 renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep23, align 1) 178 renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 179 MVE_VPST 8, implicit $vpr 180 renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4) 181 renamable $lr = t2LoopDec killed renamable $lr, 1 182 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 183 tB %bb.3, 14, $noreg 184 185 bb.3.for.cond.cleanup: 186 tPOP_RET 14, $noreg, def $r4, def $pc 187 188... 189