xref: /llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir (revision 59c6bd156cc8b42758ce90909615748e21c6eee2) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops -tail-predication=enabled %s -o - | FileCheck %s
3
4# TODOD: As far as I can tell this test is fine. The tail predicating the second loop means we remove the instruction that would otherwise block the first.
5
6--- |
7  define arm_aapcs_vfpcc void @arm_var_f32_mve(ptr %pSrc, i32 %blockSize, ptr nocapture %pResult) #0 {
8  entry:
9    %0 = add i32 %blockSize, 3
10    %1 = icmp slt i32 %blockSize, 4
11    %smin = select i1 %1, i32 %blockSize, i32 4
12    %2 = sub i32 %0, %smin
13    %3 = lshr i32 %2, 2
14    %4 = add nuw nsw i32 %3, 1
15    %5 = icmp slt i32 %blockSize, 4
16    %smin3 = select i1 %5, i32 %blockSize, i32 4
17    %6 = sub i32 %0, %smin3
18    %7 = lshr i32 %6, 2
19    %8 = add nuw nsw i32 %7, 1
20    %start1 = call i32 @llvm.start.loop.iterations.i32(i32 %8)
21    br label %do.body.i
22
23  do.body.i:                                        ; preds = %do.body.i, %entry
24    %blkCnt.0.i = phi i32 [ %13, %do.body.i ], [ %blockSize, %entry ]
25    %sumVec.0.i = phi <4 x float> [ %12, %do.body.i ], [ zeroinitializer, %entry ]
26    %pSrc.addr.0.i = phi ptr [ %add.ptr.i, %do.body.i ], [ %pSrc, %entry ]
27    %9 = phi i32 [ %start1, %entry ], [ %14, %do.body.i ]
28    %pSrc.addr.0.i2 = bitcast ptr %pSrc.addr.0.i to ptr
29    %10 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0.i)
30    %11 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr %pSrc.addr.0.i2, i32 4, <4 x i1> %10, <4 x float> zeroinitializer)
31    %12 = tail call fast <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %sumVec.0.i, <4 x float> %11, <4 x i1> %10, <4 x float> %sumVec.0.i)
32    %add.ptr.i = getelementptr inbounds float, ptr %pSrc.addr.0.i, i32 4
33    %13 = add i32 %blkCnt.0.i, -4
34    %14 = call i32 @llvm.loop.decrement.reg.i32(i32 %9, i32 1)
35    %15 = icmp ne i32 %14, 0
36    br i1 %15, label %do.body.i, label %arm_mean_f32_mve.exit
37
38  arm_mean_f32_mve.exit:                            ; preds = %do.body.i
39    %16 = extractelement <4 x float> %12, i32 3
40    %add2.i.i = fadd fast float %16, %16
41    %conv.i = uitofp i32 %blockSize to float
42    %div.i = fdiv fast float %add2.i.i, %conv.i
43    %17 = bitcast float %div.i to i32
44    %18 = insertelement <4 x i32> undef, i32 %17, i64 0
45    %19 = shufflevector <4 x i32> %18, <4 x i32> undef, <4 x i32> zeroinitializer
46    %20 = bitcast <4 x i32> %19 to <4 x float>
47    %start2 = call i32 @llvm.start.loop.iterations.i32(i32 %4)
48    br label %do.body
49
50  do.body:                                          ; preds = %do.body, %arm_mean_f32_mve.exit
51    %blkCnt.0 = phi i32 [ %blockSize, %arm_mean_f32_mve.exit ], [ %26, %do.body ]
52    %sumVec.0 = phi <4 x float> [ zeroinitializer, %arm_mean_f32_mve.exit ], [ %25, %do.body ]
53    %pSrc.addr.0 = phi ptr [ %pSrc, %arm_mean_f32_mve.exit ], [ %add.ptr, %do.body ]
54    %21 = phi i32 [ %start2, %arm_mean_f32_mve.exit ], [ %27, %do.body ]
55    %pSrc.addr.01 = bitcast ptr %pSrc.addr.0 to ptr
56    %22 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)
57    %23 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0(ptr %pSrc.addr.01, i32 4, <4 x i1> %22, <4 x float> zeroinitializer)
58    %24 = tail call fast <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %23, <4 x float> %20, <4 x i1> %22, <4 x float> undef)
59    %25 = tail call fast <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float> %24, <4 x float> %24, <4 x float> %sumVec.0, <4 x i1> %22)
60    %add.ptr = getelementptr inbounds float, ptr %pSrc.addr.0, i32 4
61    %26 = add i32 %blkCnt.0, -4
62    %27 = call i32 @llvm.loop.decrement.reg.i32(i32 %21, i32 1)
63    %28 = icmp ne i32 %27, 0
64    br i1 %28, label %do.body, label %do.end
65
66  do.end:                                           ; preds = %do.body
67    %29 = extractelement <4 x float> %25, i32 3
68    %add2.i = fadd fast float %29, %29
69    %sub2 = add i32 %blockSize, -1
70    %conv = uitofp i32 %sub2 to float
71    %div = fdiv fast float %add2.i, %conv
72    store float %div, ptr %pResult, align 4
73    ret void
74  }
75
76  declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
77
78  declare <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1
79
80  declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
81
82  declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>) #2
83
84  declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
85
86  declare i32 @llvm.start.loop.iterations.i32(i32) #3
87
88  declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #3
89
90  attributes #0 = { "target-features"="+mve.fp" }
91  attributes #1 = { nounwind readnone "target-features"="+mve.fp" }
92  attributes #2 = { argmemonly nounwind readonly willreturn "target-features"="+mve.fp" }
93  attributes #3 = { noduplicate nounwind }
94
95...
96---
97name:            arm_var_f32_mve
98alignment:       2
99exposesReturnsTwice: false
100legalized:       false
101regBankSelected: false
102selected:        false
103failedISel:      false
104tracksRegLiveness: true
105hasWinCFI:       false
106registers:       []
107liveins:
108  - { reg: '$r0', virtual-reg: '' }
109  - { reg: '$r1', virtual-reg: '' }
110  - { reg: '$r2', virtual-reg: '' }
111frameInfo:
112  isFrameAddressTaken: false
113  isReturnAddressTaken: false
114  hasStackMap:     false
115  hasPatchPoint:   false
116  stackSize:       8
117  offsetAdjustment: 0
118  maxAlignment:    4
119  adjustsStack:    false
120  hasCalls:        false
121  stackProtector:  ''
122  maxCallFrameSize: 0
123  cvBytesOfCalleeSavedRegisters: 0
124  hasOpaqueSPAdjustment: false
125  hasVAStart:      false
126  hasMustTailInVarArgFunc: false
127  localFrameSize:  0
128  savePoint:       ''
129  restorePoint:    ''
130fixedStack:      []
131stack:
132  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
133      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
134      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
135  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
136      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
137      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
138callSites:       []
139constants:       []
140machineFunctionInfo: {}
141body:             |
142  ; CHECK-LABEL: name: arm_var_f32_mve
143  ; CHECK: bb.0.entry:
144  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
145  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2, $r4
146  ; CHECK-NEXT: {{  $}}
147  ; CHECK-NEXT:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
148  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
149  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -4
150  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r4, -8
151  ; CHECK-NEXT:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
152  ; CHECK-NEXT:   $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
153  ; CHECK-NEXT:   $r12 = tMOVr $r0, 14 /* CC::al */, $noreg
154  ; CHECK-NEXT:   $lr = MVE_DLSTP_32 killed renamable $r3
155  ; CHECK-NEXT:   $r4 = tMOVr $lr, 14 /* CC::al */, $noreg
156  ; CHECK-NEXT: {{  $}}
157  ; CHECK-NEXT: bb.1.do.body.i:
158  ; CHECK-NEXT:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
159  ; CHECK-NEXT:   liveins: $lr, $q0, $r0, $r1, $r2, $r4, $r12
160  ; CHECK-NEXT: {{  $}}
161  ; CHECK-NEXT:   renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.0.i2, align 4)
162  ; CHECK-NEXT:   renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0
163  ; CHECK-NEXT:   $lr = MVE_LETP killed renamable $lr, %bb.1
164  ; CHECK-NEXT: {{  $}}
165  ; CHECK-NEXT: bb.2.arm_mean_f32_mve.exit:
166  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
167  ; CHECK-NEXT:   liveins: $q0, $r0, $r1, $r2, $r4
168  ; CHECK-NEXT: {{  $}}
169  ; CHECK-NEXT:   $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg
170  ; CHECK-NEXT:   dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg
171  ; CHECK-NEXT:   renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0
172  ; CHECK-NEXT:   $lr = t2DLS killed $r4
173  ; CHECK-NEXT:   renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg
174  ; CHECK-NEXT:   renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg
175  ; CHECK-NEXT:   renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg
176  ; CHECK-NEXT:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
177  ; CHECK-NEXT:   renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
178  ; CHECK-NEXT:   $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
179  ; CHECK-NEXT: {{  $}}
180  ; CHECK-NEXT: bb.3.do.body:
181  ; CHECK-NEXT:   successors: %bb.3(0x7c000000), %bb.4(0x04000000)
182  ; CHECK-NEXT:   liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3
183  ; CHECK-NEXT: {{  $}}
184  ; CHECK-NEXT:   renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
185  ; CHECK-NEXT:   renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
186  ; CHECK-NEXT:   MVE_VPST 2, implicit $vpr
187  ; CHECK-NEXT:   renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.01, align 4)
188  ; CHECK-NEXT:   renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2
189  ; CHECK-NEXT:   renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr, $noreg
190  ; CHECK-NEXT:   $lr = t2LEUpdate killed renamable $lr, %bb.3
191  ; CHECK-NEXT: {{  $}}
192  ; CHECK-NEXT: bb.4.do.end:
193  ; CHECK-NEXT:   liveins: $q0, $r1, $r2
194  ; CHECK-NEXT: {{  $}}
195  ; CHECK-NEXT:   renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg
196  ; CHECK-NEXT:   renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0
197  ; CHECK-NEXT:   $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg
198  ; CHECK-NEXT:   renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
199  ; CHECK-NEXT:   renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
200  ; CHECK-NEXT:   VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pResult)
201  ; CHECK-NEXT:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
202  bb.0.entry:
203    successors: %bb.1(0x80000000)
204    liveins: $r0, $r1, $r2, $r4, $lr
205
206    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
207    frame-setup CFI_INSTRUCTION def_cfa_offset 8
208    frame-setup CFI_INSTRUCTION offset $lr, -4
209    frame-setup CFI_INSTRUCTION offset $r4, -8
210    $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
211    tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
212    t2IT 10, 8, implicit-def $itstate
213    renamable $r3 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate
214    renamable $r12 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
215    renamable $r3, dead $cpsr = tSUBrr renamable $r1, killed renamable $r3, 14 /* CC::al */, $noreg
216    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
217    renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg
218    renamable $lr = nuw nsw t2ADDrs killed renamable $r12, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
219    $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
220    $r12 = tMOVr $r0, 14 /* CC::al */, $noreg
221    $lr = t2DoLoopStart renamable $lr
222    $r4 = tMOVr $lr, 14 /* CC::al */, $noreg
223
224  bb.1.do.body.i:
225    successors: %bb.1(0x7c000000), %bb.2(0x04000000)
226    liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r12
227
228    renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
229    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
230    renamable $lr = t2LoopDec killed renamable $lr, 1
231    MVE_VPST 4, implicit $vpr
232    renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.0.i2, align 4)
233    renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, renamable $q0
234    t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
235    tB %bb.2, 14 /* CC::al */, $noreg
236
237  bb.2.arm_mean_f32_mve.exit:
238    successors: %bb.3(0x80000000)
239    liveins: $q0, $r0, $r1, $r2, $r4
240
241    $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg
242    $lr = tMOVr $r4, 14 /* CC::al */, $noreg
243    renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0
244    $lr = t2DoLoopStart killed $r4
245    renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg
246    renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg
247    renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg
248    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
249    renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
250    $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
251
252  bb.3.do.body:
253    successors: %bb.3(0x7c000000), %bb.4(0x04000000)
254    liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3
255
256    renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
257    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
258    renamable $lr = t2LoopDec killed renamable $lr, 1
259    MVE_VPST 2, implicit $vpr
260    renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.01, align 4)
261    renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2
262    renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, renamable $q2, 1, killed renamable $vpr, $noreg
263    t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr
264    tB %bb.4, 14 /* CC::al */, $noreg
265
266  bb.4.do.end:
267    liveins: $q0, $r1, $r2
268
269    renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg
270    renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0
271    $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg
272    renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
273    renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
274    VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pResult)
275    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
276
277...
278