1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3 4--- | 5 define dso_local arm_aapcs_vfpcc float @insert_after_vdup_1(ptr nocapture readonly %a, ptr nocapture readonly %b, float %init, i32 %N) { 6 entry: 7 %cmp8.not = icmp eq i32 %N, 0 8 %0 = add i32 %N, 3 9 %1 = lshr i32 %0, 2 10 %2 = shl nuw i32 %1, 2 11 %3 = add i32 %2, -4 12 %4 = lshr i32 %3, 2 13 %5 = add nuw nsw i32 %4, 1 14 br i1 %cmp8.not, label %for.cond.cleanup, label %vector.ph 15 16 vector.ph: ; preds = %entry 17 %6 = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %init, i32 0 18 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 19 br label %vector.body 20 21 vector.body: ; preds = %vector.body, %vector.ph 22 %lsr.iv13 = phi ptr [ %scevgep14, %vector.body ], [ %b, %vector.ph ] 23 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 24 %vec.phi = phi <4 x float> [ %6, %vector.ph ], [ %13, %vector.body ] 25 %7 = phi i32 [ %start, %vector.ph ], [ %14, %vector.body ] 26 %8 = phi i32 [ %N, %vector.ph ], [ %10, %vector.body ] 27 %lsr.iv12 = bitcast ptr %lsr.iv to ptr 28 %lsr.iv1315 = bitcast ptr %lsr.iv13 to ptr 29 %9 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %8) 30 %10 = sub i32 %8, 4 31 %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %lsr.iv12, i32 4, <4 x i1> %9, <4 x float> undef) 32 %wide.masked.load11 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %lsr.iv1315, i32 4, <4 x i1> %9, <4 x float> undef) 33 %11 = fmul fast <4 x float> %wide.masked.load11, %wide.masked.load 34 %12 = fadd fast <4 x float> %11, %vec.phi 35 %13 = select <4 x i1> %9, <4 x float> %12, <4 x float> %vec.phi 36 %scevgep = getelementptr float, ptr %lsr.iv, i32 4 37 %scevgep14 = getelementptr float, ptr %lsr.iv13, i32 4 38 %14 = call i32 @llvm.loop.decrement.reg.i32(i32 %7, i32 1) 39 %15 = icmp ne i32 %14, 0 40 br i1 %15, label %vector.body, label %middle.block 41 42 middle.block: ; preds = %vector.body 43 %16 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.000000e+00, <4 x float> %13) 44 br label %for.cond.cleanup 45 46 for.cond.cleanup: ; preds = %middle.block, %entry 47 %res.0.lcssa = phi float [ %init, %entry ], [ %16, %middle.block ] 48 ret float %res.0.lcssa 49 } 50 51 define dso_local arm_aapcs_vfpcc float @insert_after_vdup_2(ptr nocapture readonly %a, ptr nocapture readonly %b, float %init, i32 %N) local_unnamed_addr #0 { 52 entry: 53 %shr = lshr i32 %N, 2 54 %cmp9.not = icmp eq i32 %shr, 0 55 %0 = add nuw nsw i32 %shr, 3 56 %1 = lshr i32 %0, 2 57 %2 = shl nuw nsw i32 %1, 2 58 %3 = add nsw i32 %2, -4 59 %4 = lshr i32 %3, 2 60 %5 = add nuw nsw i32 %4, 1 61 br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph 62 63 vector.ph: ; preds = %entry 64 %6 = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %init, i32 0 65 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 66 br label %vector.body 67 68 vector.body: ; preds = %vector.body, %vector.ph 69 %lsr.iv14 = phi ptr [ %scevgep15, %vector.body ], [ %b, %vector.ph ] 70 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 71 %vec.phi = phi <4 x float> [ %6, %vector.ph ], [ %13, %vector.body ] 72 %7 = phi i32 [ %start, %vector.ph ], [ %14, %vector.body ] 73 %8 = phi i32 [ %shr, %vector.ph ], [ %10, %vector.body ] 74 %lsr.iv13 = bitcast ptr %lsr.iv to ptr 75 %lsr.iv1416 = bitcast ptr %lsr.iv14 to ptr 76 %9 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %8) 77 %10 = sub i32 %8, 4 78 %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %lsr.iv13, i32 4, <4 x i1> %9, <4 x float> undef) 79 %wide.masked.load12 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %lsr.iv1416, i32 4, <4 x i1> %9, <4 x float> undef) 80 %11 = fmul fast <4 x float> %wide.masked.load12, %wide.masked.load 81 %12 = fadd fast <4 x float> %11, %vec.phi 82 %13 = select <4 x i1> %9, <4 x float> %12, <4 x float> %vec.phi 83 %scevgep = getelementptr float, ptr %lsr.iv, i32 4 84 %scevgep15 = getelementptr float, ptr %lsr.iv14, i32 4 85 %14 = call i32 @llvm.loop.decrement.reg.i32(i32 %7, i32 1) 86 %15 = icmp ne i32 %14, 0 87 br i1 %15, label %vector.body, label %middle.block 88 89 middle.block: ; preds = %vector.body 90 %16 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.000000e+00, <4 x float> %13) 91 br label %for.cond.cleanup 92 93 for.cond.cleanup: ; preds = %middle.block, %entry 94 %res.0.lcssa = phi float [ %init, %entry ], [ %16, %middle.block ] 95 ret float %res.0.lcssa 96 } 97 98 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) 99 declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>) 100 declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>) 101 declare i32 @llvm.start.loop.iterations.i32(i32) 102 declare i32 @llvm.loop.decrement.reg.i32(i32, i32) 103 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 104 105... 106--- 107name: insert_after_vdup_1 108alignment: 4 109tracksRegLiveness: true 110registers: [] 111liveins: 112 - { reg: '$r0', virtual-reg: '' } 113 - { reg: '$r1', virtual-reg: '' } 114 - { reg: '$s0', virtual-reg: '' } 115 - { reg: '$r2', virtual-reg: '' } 116frameInfo: 117 stackSize: 8 118 offsetAdjustment: 0 119 maxAlignment: 4 120 localFrameSize: 0 121 savePoint: '' 122 restorePoint: '' 123fixedStack: [] 124stack: 125 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 126 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true, 127 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 128 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 129 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 130 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 131callSites: [] 132constants: 133 - id: 0 134 value: 'float 0.000000e+00' 135 alignment: 4 136 isTargetSpecific: false 137machineFunctionInfo: {} 138body: | 139 ; CHECK-LABEL: name: insert_after_vdup_1 140 ; CHECK: bb.0.entry: 141 ; CHECK-NEXT: successors: %bb.1(0x80000000) 142 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7, $s0 143 ; CHECK-NEXT: {{ $}} 144 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 145 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 146 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $s0, implicit killed $itstate 147 ; CHECK-NEXT: {{ $}} 148 ; CHECK-NEXT: bb.1.vector.ph: 149 ; CHECK-NEXT: successors: %bb.2(0x80000000) 150 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $s0 151 ; CHECK-NEXT: {{ $}} 152 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 153 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 154 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 155 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 156 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 157 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 158 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 159 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 160 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 161 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 162 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 163 ; CHECK-NEXT: renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 164 ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 165 ; CHECK-NEXT: $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 166 ; CHECK-NEXT: {{ $}} 167 ; CHECK-NEXT: bb.2.vector.body: 168 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 169 ; CHECK-NEXT: liveins: $lr, $q1, $r0, $r1, $r2 170 ; CHECK-NEXT: {{ $}} 171 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 172 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 173 ; CHECK-NEXT: MVE_VPST 2, implicit $vpr 174 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv12, align 4) 175 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1315, align 4) 176 ; CHECK-NEXT: renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr, $noreg 177 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 178 ; CHECK-NEXT: {{ $}} 179 ; CHECK-NEXT: bb.3.middle.block: 180 ; CHECK-NEXT: liveins: $q1 181 ; CHECK-NEXT: {{ $}} 182 ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg 183 ; CHECK-NEXT: renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit killed $q1 184 ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg 185 ; CHECK-NEXT: $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr 186 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 187 ; CHECK-NEXT: {{ $}} 188 ; CHECK-NEXT: bb.4 (align 4): 189 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 4 190 bb.0.entry: 191 successors: %bb.1(0x80000000) 192 liveins: $r0, $r1, $r2, $s0, $lr 193 194 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 195 t2IT 0, 8, implicit-def $itstate 196 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $s0, implicit killed $itstate 197 198 bb.1.vector.ph: 199 successors: %bb.2(0x80000000) 200 liveins: $r0, $r1, $r2, $s0, $lr 201 202 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 203 frame-setup CFI_INSTRUCTION def_cfa_offset 8 204 frame-setup CFI_INSTRUCTION offset $lr, -4 205 frame-setup CFI_INSTRUCTION offset $r7, -8 206 $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 207 frame-setup CFI_INSTRUCTION def_cfa_register $r7 208 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 209 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 210 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 211 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 212 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 213 renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 214 $lr = t2DoLoopStart renamable $lr 215 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 216 $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 217 218 bb.2.vector.body: 219 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 220 liveins: $lr, $q1, $r0, $r1, $r2 221 222 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 223 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 224 renamable $lr = t2LoopDec killed renamable $lr, 1 225 MVE_VPST 2, implicit $vpr 226 renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv12, align 4) 227 renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1315, align 4) 228 renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr, $noreg 229 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 230 tB %bb.3, 14 /* CC::al */, $noreg 231 232 bb.3.middle.block: 233 liveins: $q1 234 235 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg 236 renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1 237 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg 238 $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr 239 tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 240 241 bb.4 (align 4): 242 CONSTPOOL_ENTRY 0, %const.0, 4 243 244... 245--- 246name: insert_after_vdup_2 247alignment: 4 248tracksRegLiveness: true 249registers: [] 250liveins: 251 - { reg: '$r0', virtual-reg: '' } 252 - { reg: '$r1', virtual-reg: '' } 253 - { reg: '$s0', virtual-reg: '' } 254 - { reg: '$r2', virtual-reg: '' } 255frameInfo: 256 stackSize: 8 257 offsetAdjustment: 0 258 maxAlignment: 4 259 savePoint: '' 260 restorePoint: '' 261fixedStack: [] 262stack: 263 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 264 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true, 265 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 266 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 267 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 268 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 269callSites: [] 270constants: 271 - id: 0 272 value: 'float 0.000000e+00' 273 alignment: 4 274 isTargetSpecific: false 275machineFunctionInfo: {} 276body: | 277 ; CHECK-LABEL: name: insert_after_vdup_2 278 ; CHECK: bb.0.entry: 279 ; CHECK-NEXT: successors: %bb.1(0x80000000) 280 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7, $s0 281 ; CHECK-NEXT: {{ $}} 282 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 283 ; CHECK-NEXT: t2CMPrs killed renamable $r3, renamable $r2, 19, 14 /* CC::al */, $noreg, implicit-def $cpsr 284 ; CHECK-NEXT: t2IT 0, 8, implicit-def $itstate 285 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $s0, implicit killed $itstate 286 ; CHECK-NEXT: {{ $}} 287 ; CHECK-NEXT: bb.1.vector.ph: 288 ; CHECK-NEXT: successors: %bb.2(0x80000000) 289 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $s0 290 ; CHECK-NEXT: {{ $}} 291 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 292 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 293 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 294 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 295 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 296 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 297 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg 298 ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 299 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 300 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 301 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 302 ; CHECK-NEXT: renamable $lr = t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 303 ; CHECK-NEXT: renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 304 ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 305 ; CHECK-NEXT: renamable $r2, dead $cpsr = tLSRri killed renamable $r2, 2, 14 /* CC::al */, $noreg 306 ; CHECK-NEXT: $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 307 ; CHECK-NEXT: {{ $}} 308 ; CHECK-NEXT: bb.2.vector.body: 309 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 310 ; CHECK-NEXT: liveins: $lr, $q1, $r0, $r1, $r2 311 ; CHECK-NEXT: {{ $}} 312 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 313 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 314 ; CHECK-NEXT: MVE_VPST 2, implicit $vpr 315 ; CHECK-NEXT: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) 316 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) 317 ; CHECK-NEXT: renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr, $noreg 318 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 319 ; CHECK-NEXT: {{ $}} 320 ; CHECK-NEXT: bb.3.middle.block: 321 ; CHECK-NEXT: liveins: $q1 322 ; CHECK-NEXT: {{ $}} 323 ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg 324 ; CHECK-NEXT: renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit killed $q1 325 ; CHECK-NEXT: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg 326 ; CHECK-NEXT: $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr 327 ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 328 ; CHECK-NEXT: {{ $}} 329 ; CHECK-NEXT: bb.4 (align 4): 330 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 4 331 bb.0.entry: 332 successors: %bb.1(0x80000000) 333 liveins: $r0, $r1, $r2, $s0, $lr 334 335 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 336 t2CMPrs killed renamable $r3, renamable $r2, 19, 14 /* CC::al */, $noreg, implicit-def $cpsr 337 t2IT 0, 8, implicit-def $itstate 338 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $s0, implicit killed $itstate 339 340 bb.1.vector.ph: 341 successors: %bb.2(0x80000000) 342 liveins: $r0, $r1, $r2, $s0, $lr 343 344 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 345 frame-setup CFI_INSTRUCTION def_cfa_offset 8 346 frame-setup CFI_INSTRUCTION offset $lr, -4 347 frame-setup CFI_INSTRUCTION offset $r7, -8 348 $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 349 frame-setup CFI_INSTRUCTION def_cfa_register $r7 350 renamable $r3, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg 351 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 352 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 353 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 354 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 355 renamable $lr = t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 356 renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 357 $lr = t2DoLoopStart renamable $lr 358 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 359 renamable $r2, dead $cpsr = tLSRri killed renamable $r2, 2, 14 /* CC::al */, $noreg 360 $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 361 362 bb.2.vector.body: 363 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 364 liveins: $lr, $q1, $r0, $r1, $r2 365 366 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 367 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 368 renamable $lr = t2LoopDec killed renamable $lr, 1 369 MVE_VPST 2, implicit $vpr 370 renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) 371 renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) 372 renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr, $noreg 373 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 374 tB %bb.3, 14 /* CC::al */, $noreg 375 376 bb.3.middle.block: 377 liveins: $q1 378 379 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg 380 renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1 381 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg 382 $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr 383 tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 384 385 bb.4 (align 4): 386 CONSTPOOL_ENTRY 0, %const.0, 4 387 388... 389