1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s 3 4--- | 5 define dso_local arm_aapcs_vfpcc void @test(ptr noalias nocapture %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 { 6 entry: 7 %cmp9 = icmp eq i32 %N, 0 8 %tmp = add i32 %N, 3 9 %tmp1 = lshr i32 %tmp, 2 10 %tmp2 = shl nuw i32 %tmp1, 2 11 %tmp3 = add i32 %tmp2, -4 12 %tmp4 = lshr i32 %tmp3, 2 13 %tmp5 = add nuw nsw i32 %tmp4, 1 14 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph 15 16 vector.ph: ; preds = %entry 17 %div = lshr i32 %N, 1 18 %trip.count.minus.1 = add i32 %N, -1 19 %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0 20 %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 21 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 22 br label %vector.body 23 24 vector.body: ; preds = %vector.body, %vector.ph 25 %lsr.iv = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 26 %lsr.iv3 = phi ptr [ %scevgep4, %vector.body ], [ %b, %vector.ph ] 27 %lsr.iv1 = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 28 %vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %vector.ph ], [ %vec.ind.next, %vector.body ] 29 %elts.rem = phi i32 [ %N, %vector.ph ], [ %elts.rem.next, %vector.body ] 30 %lsr.iv12 = bitcast ptr %lsr.iv1 to ptr 31 %lsr.iv35 = bitcast ptr %lsr.iv3 to ptr 32 %tmp7 = insertelement <4 x i32> undef, i32 %div, i32 0 33 %tmp8 = shufflevector <4 x i32> %tmp7, <4 x i32> undef, <4 x i32> zeroinitializer 34 %tmp9 = icmp ult <4 x i32> %vec.ind, %tmp8 35 %lower = icmp uge <4 x i32> %vec.ind, <i32 1, i32 1, i32 1, i32 1> 36 %tmp10 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %elts.rem) 37 %tmp11 = and <4 x i1> %tmp9, %tmp10 38 %pred = and <4 x i1> %tmp11, %lower 39 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv35, i32 4, <4 x i1> %pred, <4 x i32> undef) 40 call void @llvm.masked.store.v4i32.p0(<4 x i32> %wide.masked.load, ptr %lsr.iv12, i32 4, <4 x i1> %pred) 41 %vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4> 42 %elts.rem.next = sub i32 %elts.rem, 4 43 %scevgep = getelementptr i32, ptr %lsr.iv1, i32 4 44 %scevgep4 = getelementptr i32, ptr %lsr.iv3, i32 4 45 %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1) 46 %tmp13 = icmp ne i32 %tmp12, 0 47 %lsr.iv.next = add nsw i32 %lsr.iv, -1 48 br i1 %tmp13, label %vector.body, label %for.cond.cleanup 49 50 for.cond.cleanup: ; preds = %vector.body, %entry 51 ret void 52 } 53 54 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) 55 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) 56 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 57 declare i32 @llvm.start.loop.iterations.i32(i32) 58 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 59... 60--- 61name: test 62alignment: 16 63tracksRegLiveness: true 64registers: [] 65liveins: 66 - { reg: '$r0', virtual-reg: '' } 67 - { reg: '$r1', virtual-reg: '' } 68 - { reg: '$r2', virtual-reg: '' } 69frameInfo: 70 stackSize: 24 71 offsetAdjustment: 0 72 maxAlignment: 8 73fixedStack: [] 74stack: 75 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 76 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 77 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 78 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 79 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 80 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 81 - { id: 2, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8, 82 stack-id: default, callee-saved-register: '$d9', callee-saved-restored: true, 83 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 84 - { id: 3, name: '', type: spill-slot, offset: -24, size: 8, alignment: 8, 85 stack-id: default, callee-saved-register: '$d8', callee-saved-restored: true, 86 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 87callSites: [] 88constants: 89 - id: 0 90 value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>' 91 alignment: 16 92 isTargetSpecific: false 93machineFunctionInfo: {} 94body: | 95 ; CHECK-LABEL: name: test 96 ; CHECK: bb.0.entry: 97 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) 98 ; CHECK-NEXT: liveins: $lr, $d8, $d9, $r0, $r1, $r2, $r4 99 ; CHECK-NEXT: {{ $}} 100 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 101 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 102 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 103 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -8 104 ; CHECK-NEXT: $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9 105 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 24 106 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $d9, -16 107 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $d8, -24 108 ; CHECK-NEXT: tCBZ $r2, %bb.3 109 ; CHECK-NEXT: {{ $}} 110 ; CHECK-NEXT: bb.1.vector.ph: 111 ; CHECK-NEXT: successors: %bb.2(0x80000000) 112 ; CHECK-NEXT: liveins: $r0, $r1, $r2 113 ; CHECK-NEXT: {{ $}} 114 ; CHECK-NEXT: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 115 ; CHECK-NEXT: renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2 116 ; CHECK-NEXT: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 117 ; CHECK-NEXT: renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3 118 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 119 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 120 ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 121 ; CHECK-NEXT: dead $lr = t2DLS renamable $r3 122 ; CHECK-NEXT: $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg 123 ; CHECK-NEXT: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg 124 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) 125 ; CHECK-NEXT: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg 126 ; CHECK-NEXT: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 127 ; CHECK-NEXT: {{ $}} 128 ; CHECK-NEXT: bb.2.vector.body: 129 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 130 ; CHECK-NEXT: liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4 131 ; CHECK-NEXT: {{ $}} 132 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 133 ; CHECK-NEXT: $lr = tMOVr $r4, 14 /* CC::al */, $noreg 134 ; CHECK-NEXT: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 135 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 136 ; CHECK-NEXT: MVE_VPST 1, implicit $vpr 137 ; CHECK-NEXT: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr, $noreg 138 ; CHECK-NEXT: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg 139 ; CHECK-NEXT: renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4) 140 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4) 141 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0 142 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 143 ; CHECK-NEXT: {{ $}} 144 ; CHECK-NEXT: bb.3.for.cond.cleanup: 145 ; CHECK-NEXT: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9 146 ; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 147 ; CHECK-NEXT: {{ $}} 148 ; CHECK-NEXT: bb.4 (align 16): 149 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16 150 bb.0.entry: 151 successors: %bb.3(0x30000000), %bb.1(0x50000000) 152 liveins: $r0, $r1, $r2, $r4, $lr, $d8, $d9 153 154 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp 155 frame-setup CFI_INSTRUCTION def_cfa_offset 8 156 frame-setup CFI_INSTRUCTION offset $lr, -4 157 frame-setup CFI_INSTRUCTION offset $r4, -8 158 $sp = frame-setup VSTMDDB_UPD $sp, 14 /* CC::al */, $noreg, killed $d8, killed $d9 159 frame-setup CFI_INSTRUCTION def_cfa_offset 24 160 frame-setup CFI_INSTRUCTION offset $d9, -16 161 frame-setup CFI_INSTRUCTION offset $d8, -24 162 tCBZ $r2, %bb.3 163 164 bb.1.vector.ph: 165 successors: %bb.2(0x80000000) 166 liveins: $r0, $r1, $r2 167 168 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 169 renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2 170 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 171 renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3 172 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 173 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 174 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 175 $lr = t2DoLoopStart renamable $r3 176 $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg 177 renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg 178 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) 179 renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg 180 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 181 182 bb.2.vector.body: 183 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 184 liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4 185 186 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 187 $lr = tMOVr $r4, 14 /* CC::al */, $noreg 188 renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg 189 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 190 MVE_VPST 1, implicit $vpr 191 renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr, $noreg 192 renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg 193 renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4) 194 renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4) 195 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0 196 renamable $lr = t2LoopDec killed renamable $lr, 1 197 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 198 tB %bb.3, 14 /* CC::al */, $noreg 199 200 bb.3.for.cond.cleanup: 201 $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9 202 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc 203 204 bb.4 (align 16): 205 CONSTPOOL_ENTRY 0, %const.0, 16 206 207... 208