1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s 3 4# IT-block with 2 statements, which we don't support yet, so check that we do 5# not remove any of the iteration count statements. 6 7--- | 8 define hidden arm_aapcs_vfpcc void @it_block_2_stmts(ptr %pSrc, ptr %pDst, i32 %blockSize) local_unnamed_addr #0 { 9 entry: 10 %mul = shl i32 %blockSize, 1 11 %0 = add i32 %mul, 3 12 %1 = icmp slt i32 %mul, 4 13 %smin = select i1 %1, i32 %mul, i32 4 14 %2 = sub i32 %0, %smin 15 %3 = lshr i32 %2, 2 16 %4 = add nuw nsw i32 %3, 1 17 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4) 18 br label %do.body 19 20 do.body: ; preds = %do.body, %entry 21 %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ] 22 %pDst.addr.0 = phi ptr [ %pDst, %entry ], [ %add.ptr4, %do.body ] 23 %pSrc.addr.0 = phi ptr [ %pSrc, %entry ], [ %add.ptr, %do.body ] 24 %5 = phi i32 [ %start, %entry ], [ %9, %do.body ] 25 %6 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0) 26 %7 = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %pSrc.addr.0, i32 4, <4 x i1> %6, <4 x float> undef) 27 %8 = fmul <4 x float> %7, <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00> 28 tail call void @llvm.masked.store.v4f32.p0(<4 x float> %8, ptr %pDst.addr.0, i32 4, <4 x i1> %6) 29 %add.ptr = getelementptr inbounds float, ptr %pSrc.addr.0, i32 4 30 %add.ptr4 = getelementptr inbounds float, ptr %pDst.addr.0, i32 4 31 %sub = add nsw i32 %blkCnt.0, -4 32 %9 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) 33 %10 = icmp ne i32 %9, 0 34 br i1 %10, label %do.body, label %do.end 35 36 do.end: ; preds = %do.body 37 ret void 38 } 39 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1 40 declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>) 41 declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32 immarg, <4 x i1>) 42 declare i32 @llvm.start.loop.iterations.i32(i32) 43 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 44 45... 46--- 47name: it_block_2_stmts 48alignment: 16 49exposesReturnsTwice: false 50legalized: false 51regBankSelected: false 52selected: false 53failedISel: false 54tracksRegLiveness: true 55hasWinCFI: false 56registers: [] 57liveins: 58 - { reg: '$r0', virtual-reg: '' } 59 - { reg: '$r1', virtual-reg: '' } 60 - { reg: '$r2', virtual-reg: '' } 61frameInfo: 62 isFrameAddressTaken: false 63 isReturnAddressTaken: false 64 hasStackMap: false 65 hasPatchPoint: false 66 stackSize: 8 67 offsetAdjustment: 0 68 maxAlignment: 4 69 adjustsStack: false 70 hasCalls: false 71 stackProtector: '' 72 maxCallFrameSize: 0 73 cvBytesOfCalleeSavedRegisters: 0 74 hasOpaqueSPAdjustment: false 75 hasVAStart: false 76 hasMustTailInVarArgFunc: false 77 localFrameSize: 0 78 savePoint: '' 79 restorePoint: '' 80fixedStack: [] 81stack: 82 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 83 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 84 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 85 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 86 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 87 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 88callSites: [] 89constants: 90 - id: 0 91 value: '<4 x float> <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>' 92 alignment: 16 93 isTargetSpecific: false 94machineFunctionInfo: {} 95body: | 96 ; CHECK-LABEL: name: it_block_2_stmts 97 ; CHECK: bb.0.entry: 98 ; CHECK-NEXT: successors: %bb.1(0x80000000) 99 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 100 ; CHECK-NEXT: {{ $}} 101 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 102 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 103 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 104 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 105 ; CHECK-NEXT: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg 106 ; CHECK-NEXT: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg 107 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) 108 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3 109 ; CHECK-NEXT: {{ $}} 110 ; CHECK-NEXT: bb.1.do.body (align 4): 111 ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000) 112 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1 113 ; CHECK-NEXT: {{ $}} 114 ; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg, $noreg 115 ; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 116 ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg, $noreg 117 ; CHECK-NEXT: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg 118 ; CHECK-NEXT: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg 119 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.1 120 ; CHECK-NEXT: {{ $}} 121 ; CHECK-NEXT: bb.2.do.end: 122 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 123 ; CHECK-NEXT: {{ $}} 124 ; CHECK-NEXT: bb.3 (align 16): 125 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16 126 bb.0.entry: 127 successors: %bb.1(0x80000000) 128 liveins: $r0, $r1, $r2, $r7, $lr 129 130 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 131 frame-setup CFI_INSTRUCTION def_cfa_offset 8 132 frame-setup CFI_INSTRUCTION offset $lr, -4 133 frame-setup CFI_INSTRUCTION offset $r7, -8 134 renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg 135 renamable $r12 = t2MOVi 4, 14, $noreg, $noreg 136 tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr 137 t2IT 11, 8, implicit-def $itstate 138 $r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate 139 $r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate 140 renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg 141 renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg 142 renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg 143 renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg 144 renamable $r2 = tLEApcrel %const.0, 14, $noreg 145 renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) 146 $lr = t2DoLoopStart renamable $lr 147 148 bb.1.do.body (align 4): 149 successors: %bb.1(0x7c000000), %bb.2(0x04000000) 150 liveins: $lr, $q0, $r0, $r1, $r3 151 152 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg 153 MVE_VPST 2, implicit $vpr 154 renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg 155 renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q1 156 MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr, $noreg 157 renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg 158 renamable $lr = t2LoopDec killed renamable $lr, 1 159 renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg 160 renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg 161 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr 162 tB %bb.2, 14, $noreg 163 164 bb.2.do.end: 165 tPOP_RET 14, $noreg, def $r7, def $pc 166 167 bb.3 (align 16): 168 CONSTPOOL_ENTRY 0, %const.0, 16 169 170... 171