1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s 3 4# IT-block with 3 statements, all chained together. 5 6--- | 7 define hidden arm_aapcs_vfpcc void @it_block_2_stmts(ptr %pSrc, ptr %pDst, i32 %blockSize) local_unnamed_addr #0 { 8 entry: 9 %mul = shl i32 %blockSize, 1 10 %0 = add i32 %mul, 3 11 %1 = icmp slt i32 %mul, 4 12 %smin = select i1 %1, i32 %mul, i32 4 13 %2 = sub i32 %0, %smin 14 %3 = lshr i32 %2, 2 15 %4 = add nuw nsw i32 %3, 1 16 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4) 17 br label %do.body 18 19 do.body: ; preds = %do.body, %entry 20 %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ] 21 %pDst.addr.0 = phi ptr [ %pDst, %entry ], [ %add.ptr4, %do.body ] 22 %pSrc.addr.0 = phi ptr [ %pSrc, %entry ], [ %add.ptr, %do.body ] 23 %5 = phi i32 [ %start, %entry ], [ %9, %do.body ] 24 %6 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0) 25 %7 = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %pSrc.addr.0, i32 4, <4 x i1> %6, <4 x float> undef) 26 %8 = fmul <4 x float> %7, <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00> 27 tail call void @llvm.masked.store.v4f32.p0(<4 x float> %8, ptr %pDst.addr.0, i32 4, <4 x i1> %6) 28 %add.ptr = getelementptr inbounds float, ptr %pSrc.addr.0, i32 4 29 %add.ptr4 = getelementptr inbounds float, ptr %pDst.addr.0, i32 4 30 %sub = add nsw i32 %blkCnt.0, -4 31 %9 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) 32 %10 = icmp ne i32 %9, 0 33 br i1 %10, label %do.body, label %do.end 34 35 do.end: ; preds = %do.body 36 ret void 37 } 38 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1 39 declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>) 40 declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32 immarg, <4 x i1>) 41 declare i32 @llvm.start.loop.iterations.i32(i32) 42 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 43 44... 45--- 46name: it_block_2_stmts 47alignment: 16 48exposesReturnsTwice: false 49legalized: false 50regBankSelected: false 51selected: false 52failedISel: false 53tracksRegLiveness: true 54hasWinCFI: false 55registers: [] 56liveins: 57 - { reg: '$r0', virtual-reg: '' } 58 - { reg: '$r1', virtual-reg: '' } 59 - { reg: '$r2', virtual-reg: '' } 60frameInfo: 61 isFrameAddressTaken: false 62 isReturnAddressTaken: false 63 hasStackMap: false 64 hasPatchPoint: false 65 stackSize: 8 66 offsetAdjustment: 0 67 maxAlignment: 4 68 adjustsStack: false 69 hasCalls: false 70 stackProtector: '' 71 maxCallFrameSize: 0 72 cvBytesOfCalleeSavedRegisters: 0 73 hasOpaqueSPAdjustment: false 74 hasVAStart: false 75 hasMustTailInVarArgFunc: false 76 localFrameSize: 0 77 savePoint: '' 78 restorePoint: '' 79fixedStack: [] 80stack: 81 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 82 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 83 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 84 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 85 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 86 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 87callSites: [] 88constants: 89 - id: 0 90 value: '<4 x float> <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>' 91 alignment: 16 92 isTargetSpecific: false 93machineFunctionInfo: {} 94body: | 95 ; CHECK-LABEL: name: it_block_2_stmts 96 ; CHECK: bb.0.entry: 97 ; CHECK-NEXT: successors: %bb.1(0x80000000) 98 ; CHECK-NEXT: liveins: $lr, $r0, $r2, $r7 99 ; CHECK-NEXT: {{ $}} 100 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 101 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 102 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 103 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 104 ; CHECK-NEXT: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14 /* CC::al */, $noreg 105 ; CHECK-NEXT: renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg 106 ; CHECK-NEXT: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr 107 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 108 ; CHECK-NEXT: $r1 = t2ADDri renamable $r0, 3, 11 /* CC::lt */, $noreg, $noreg, implicit $itstate 109 ; CHECK-NEXT: $r3 = t2LSLri renamable $r2, 1, 11 /* CC::lt */, $cpsr, $noreg, implicit renamable $r12, implicit $itstate 110 ; CHECK-NEXT: $r12 = t2LSLri renamable $r3, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate 111 ; CHECK-NEXT: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg 112 ; CHECK-NEXT: dead renamable $r12 = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg 113 ; CHECK-NEXT: dead renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 114 ; CHECK-NEXT: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg 115 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) 116 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3 117 ; CHECK-NEXT: {{ $}} 118 ; CHECK-NEXT: bb.1.do.body (align 4): 119 ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000) 120 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1 121 ; CHECK-NEXT: {{ $}} 122 ; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg, $noreg 123 ; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1 124 ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg, $noreg 125 ; CHECK-NEXT: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg 126 ; CHECK-NEXT: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg 127 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.1 128 ; CHECK-NEXT: {{ $}} 129 ; CHECK-NEXT: bb.2.do.end: 130 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 131 ; CHECK-NEXT: {{ $}} 132 ; CHECK-NEXT: bb.3 (align 16): 133 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16 134 bb.0.entry: 135 successors: %bb.1(0x80000000) 136 liveins: $r0, $r1, $r2, $r7, $lr 137 138 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 139 frame-setup CFI_INSTRUCTION def_cfa_offset 8 140 frame-setup CFI_INSTRUCTION offset $lr, -4 141 frame-setup CFI_INSTRUCTION offset $r7, -8 142 renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg 143 renamable $r12 = t2MOVi 4, 14, $noreg, $noreg 144 tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr 145 t2IT 11, 8, implicit-def $itstate 146 $r1 = t2ADDri renamable $r0, 3, 11, $noreg, $noreg, implicit $itstate 147 $r3 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate 148 $r12 = t2LSLri renamable $r3, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate 149 renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg 150 renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg 151 renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg 152 renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg 153 renamable $r2 = tLEApcrel %const.0, 14, $noreg 154 renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) 155 $lr = t2DoLoopStart renamable $lr 156 157 bb.1.do.body (align 4): 158 successors: %bb.1(0x7c000000), %bb.2(0x04000000) 159 liveins: $lr, $q0, $r0, $r1, $r3 160 161 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg 162 MVE_VPST 2, implicit $vpr 163 renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg 164 renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q1 165 MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr, $noreg 166 renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg 167 renamable $lr = t2LoopDec killed renamable $lr, 1 168 renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg 169 renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg 170 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr 171 tB %bb.2, 14, $noreg 172 173 bb.2.do.end: 174 tPOP_RET 14, $noreg, def $r7, def $pc 175 176 bb.3 (align 16): 177 CONSTPOOL_ENTRY 0, %const.0, 16 178 179... 180