1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3 4--- | 5 define dso_local <4 x i32> @invariant_use_store(ptr nocapture readonly %a, ptr %c, i32 %N, <4 x i32> %pass) { 6 entry: 7 %cmp9 = icmp eq i32 %N, 0 8 %tmp = add i32 %N, 3 9 %tmp1 = lshr i32 %tmp, 2 10 %tmp2 = shl nuw i32 %tmp1, 2 11 %tmp3 = add i32 %tmp2, -4 12 %tmp4 = lshr i32 %tmp3, 2 13 %tmp5 = add nuw nsw i32 %tmp4, 1 14 br i1 %cmp9, label %exit, label %vector.ph 15 16 vector.ph: ; preds = %entry 17 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 18 br label %vector.body 19 20 vector.body: ; preds = %vector.body, %vector.ph 21 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 22 %lsr.iv20 = phi ptr [ %scevgep20, %vector.body ], [ %c, %vector.ph ] 23 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 24 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp13, %vector.body ] 25 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 26 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 27 %lsr.store = bitcast ptr %lsr.iv20 to ptr 28 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 29 %tmp9 = sub i32 %tmp7, 4 30 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 31 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> 32 %tmp12 = mul nsw <4 x i32> %pass, %tmp10 33 %tmp13 = add <4 x i32> %tmp12, %vec.phi 34 call void @llvm.masked.store.v4i32.p0(<4 x i32> %tmp13, ptr %lsr.store, i32 4, <4 x i1> %tmp8) 35 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4 36 %scevgep20 = getelementptr i32, ptr %lsr.iv20, i32 4 37 %tmp14 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 38 %tmp15 = icmp ne i32 %tmp14, 0 39 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 40 br i1 %tmp15, label %vector.body, label %exit 41 42 exit: ; preds = %vector.body, %entry 43 ret <4 x i32> %pass 44 } 45 46 define dso_local i32 @invariant_mul_use_reduce(ptr nocapture readonly %a, ptr %c, i32 %N, <4 x i32> %pass) { 47 entry: 48 %cmp9 = icmp eq i32 %N, 0 49 %tmp = add i32 %N, 3 50 %tmp1 = lshr i32 %tmp, 2 51 %tmp2 = shl nuw i32 %tmp1, 2 52 %tmp3 = add i32 %tmp2, -4 53 %tmp4 = lshr i32 %tmp3, 2 54 %tmp5 = add nuw nsw i32 %tmp4, 1 55 br i1 %cmp9, label %exit, label %vector.ph 56 57 vector.ph: ; preds = %entry 58 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 59 br label %vector.body 60 61 vector.body: ; preds = %vector.body, %vector.ph 62 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 63 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 64 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 65 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 66 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 67 %tmp9 = sub i32 %tmp7, 4 68 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 69 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> 70 %tmp12 = mul nsw <4 x i32> %pass, %tmp10 71 %tmp13 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp12) 72 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4 73 %tmp15 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 74 %tmp16 = icmp ne i32 %tmp15, 0 75 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 76 br i1 %tmp16, label %vector.body, label %exit 77 78 exit: ; preds = %vector.body, %entry 79 %res = phi i32 [ 0, %entry ], [ %tmp13, %vector.body ] 80 ret i32 %res 81 } 82 83 define dso_local i32 @invariant_add_use_reduce(ptr nocapture readonly %a, ptr %c, i32 %N, <4 x i32> %pass) { 84 entry: 85 %cmp9 = icmp eq i32 %N, 0 86 %tmp = add i32 %N, 3 87 %tmp1 = lshr i32 %tmp, 2 88 %tmp2 = shl nuw i32 %tmp1, 2 89 %tmp3 = add i32 %tmp2, -4 90 %tmp4 = lshr i32 %tmp3, 2 91 %tmp5 = add nuw nsw i32 %tmp4, 1 92 br i1 %cmp9, label %exit, label %vector.ph 93 94 vector.ph: ; preds = %entry 95 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 96 br label %vector.body 97 98 vector.body: ; preds = %vector.body, %vector.ph 99 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 100 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 101 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 102 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 103 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 104 %tmp9 = sub i32 %tmp7, 4 105 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 106 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> 107 %tmp12 = add nsw <4 x i32> %pass, %tmp10 108 %tmp13 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp12) 109 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4 110 %tmp15 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 111 %tmp16 = icmp ne i32 %tmp15, 0 112 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 113 br i1 %tmp16, label %vector.body, label %exit 114 115 exit: ; preds = %vector.body, %entry 116 %res = phi i32 [ 0, %entry ], [ %tmp13, %vector.body ] 117 ret i32 %res 118 } 119 120 declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) 121 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>) 122 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) 123 declare i32 @llvm.start.loop.iterations.i32(i32) 124 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 125 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 126 127... 128--- 129name: invariant_use_store 130alignment: 2 131tracksRegLiveness: true 132registers: [] 133liveins: 134 - { reg: '$r0', virtual-reg: '' } 135 - { reg: '$r1', virtual-reg: '' } 136 - { reg: '$r2', virtual-reg: '' } 137frameInfo: 138 stackSize: 8 139 offsetAdjustment: 0 140 maxAlignment: 8 141fixedStack: 142 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, 143 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 144 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 145stack: 146 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 147 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 148 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 149 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 150 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 151 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 152callSites: [] 153constants: [] 154machineFunctionInfo: {} 155body: | 156 ; CHECK-LABEL: name: invariant_use_store 157 ; CHECK: bb.0.entry: 158 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.1(0x50000000) 159 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 160 ; CHECK-NEXT: {{ $}} 161 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 162 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 163 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 164 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 165 ; CHECK-NEXT: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 166 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) 167 ; CHECK-NEXT: tCBZ $r2, %bb.3 168 ; CHECK-NEXT: {{ $}} 169 ; CHECK-NEXT: bb.1.vector.ph: 170 ; CHECK-NEXT: successors: %bb.2(0x80000000) 171 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2 172 ; CHECK-NEXT: {{ $}} 173 ; CHECK-NEXT: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 174 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 175 ; CHECK-NEXT: {{ $}} 176 ; CHECK-NEXT: bb.2.vector.body: 177 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 178 ; CHECK-NEXT: liveins: $lr, $q0, $q1, $r0, $r1 179 ; CHECK-NEXT: {{ $}} 180 ; CHECK-NEXT: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 181 ; CHECK-NEXT: renamable $q2 = nsw MVE_VMULi32 renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 182 ; CHECK-NEXT: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 183 ; CHECK-NEXT: renamable $r1 = MVE_VSTRWU32_post renamable $q1, killed renamable $r1, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.store, align 4) 184 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 185 ; CHECK-NEXT: {{ $}} 186 ; CHECK-NEXT: bb.3.exit: 187 ; CHECK-NEXT: liveins: $q0 188 ; CHECK-NEXT: {{ $}} 189 ; CHECK-NEXT: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg 190 ; CHECK-NEXT: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit killed $q0 191 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 192 bb.0.entry: 193 successors: %bb.3(0x30000000), %bb.1(0x50000000) 194 liveins: $r0, $r1, $r2, $r7, $lr 195 196 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 197 frame-setup CFI_INSTRUCTION def_cfa_offset 8 198 frame-setup CFI_INSTRUCTION offset $lr, -4 199 frame-setup CFI_INSTRUCTION offset $r7, -8 200 renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 201 renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) 202 tCBZ $r2, %bb.3 203 204 bb.1.vector.ph: 205 successors: %bb.2(0x80000000) 206 liveins: $q0, $r0, $r1, $r2 207 208 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 209 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1 210 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 211 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 212 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 213 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 214 $lr = t2DoLoopStart renamable $r12 215 $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg 216 217 bb.2.vector.body: 218 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 219 liveins: $q0, $q1, $r0, $r1, $r2, $r3 220 221 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 222 MVE_VPST 8, implicit $vpr 223 renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 224 $lr = tMOVr $r3, 14 /* CC::al */, $noreg 225 renamable $q2 = nsw MVE_VMULi32 renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2 226 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 227 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 228 renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 229 renamable $lr = t2LoopDec killed renamable $lr, 1 230 MVE_VPST 8, implicit $vpr 231 renamable $r1 = MVE_VSTRWU32_post renamable $q1, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.store, align 4) 232 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 233 tB %bb.3, 14 /* CC::al */, $noreg 234 235 bb.3.exit: 236 liveins: $q0 237 238 renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg 239 renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit $q0 240 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 241 242... 243--- 244name: invariant_mul_use_reduce 245alignment: 2 246tracksRegLiveness: true 247registers: [] 248liveins: 249 - { reg: '$r0', virtual-reg: '' } 250 - { reg: '$r2', virtual-reg: '' } 251frameInfo: 252 stackSize: 8 253 offsetAdjustment: 0 254 maxAlignment: 8 255fixedStack: 256 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, 257 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 258 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 259stack: 260 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 261 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 262 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 263 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 264 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 265 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 266callSites: [] 267constants: [] 268machineFunctionInfo: {} 269body: | 270 ; CHECK-LABEL: name: invariant_mul_use_reduce 271 ; CHECK: bb.0.entry: 272 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) 273 ; CHECK-NEXT: liveins: $lr, $r0, $r2, $r7 274 ; CHECK-NEXT: {{ $}} 275 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 276 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 277 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 278 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 279 ; CHECK-NEXT: tCBZ $r2, %bb.4 280 ; CHECK-NEXT: {{ $}} 281 ; CHECK-NEXT: bb.1.vector.ph: 282 ; CHECK-NEXT: successors: %bb.2(0x80000000) 283 ; CHECK-NEXT: liveins: $r0, $r2 284 ; CHECK-NEXT: {{ $}} 285 ; CHECK-NEXT: renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 286 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 287 ; CHECK-NEXT: renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg 288 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 289 ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg 290 ; CHECK-NEXT: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 291 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) 292 ; CHECK-NEXT: dead $lr = t2DLS renamable $r3 293 ; CHECK-NEXT: $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg 294 ; CHECK-NEXT: {{ $}} 295 ; CHECK-NEXT: bb.2.vector.body: 296 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 297 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2 298 ; CHECK-NEXT: {{ $}} 299 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 300 ; CHECK-NEXT: $lr = tMOVr $r1, 14 /* CC::al */, $noreg 301 ; CHECK-NEXT: renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg 302 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 303 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 304 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 305 ; CHECK-NEXT: renamable $r12 = MVE_VMLADAVu32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg 306 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 307 ; CHECK-NEXT: {{ $}} 308 ; CHECK-NEXT: bb.3.exit: 309 ; CHECK-NEXT: liveins: $r12 310 ; CHECK-NEXT: {{ $}} 311 ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 312 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 313 ; CHECK-NEXT: {{ $}} 314 ; CHECK-NEXT: bb.4: 315 ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 316 ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 317 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 318 bb.0.entry: 319 successors: %bb.4(0x30000000), %bb.1(0x50000000) 320 liveins: $r0, $r2, $r7, $lr 321 322 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 323 frame-setup CFI_INSTRUCTION def_cfa_offset 8 324 frame-setup CFI_INSTRUCTION offset $lr, -4 325 frame-setup CFI_INSTRUCTION offset $r7, -8 326 tCBZ $r2, %bb.4 327 328 bb.1.vector.ph: 329 successors: %bb.2(0x80000000) 330 liveins: $r0, $r2 331 332 renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 333 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 334 renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg 335 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 336 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg 337 renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 338 renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) 339 $lr = t2DoLoopStart renamable $r3 340 $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg 341 342 bb.2.vector.body: 343 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 344 liveins: $q0, $r0, $r1, $r2 345 346 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 347 $lr = tMOVr $r1, 14 /* CC::al */, $noreg 348 renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg 349 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 350 MVE_VPST 8, implicit $vpr 351 renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 352 renamable $r12 = MVE_VMLADAVu32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg 353 renamable $lr = t2LoopDec killed renamable $lr, 1 354 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 355 tB %bb.3, 14 /* CC::al */, $noreg 356 357 bb.3.exit: 358 liveins: $r12 359 360 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 361 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 362 363 bb.4: 364 renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 365 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 366 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 367 368... 369--- 370name: invariant_add_use_reduce 371alignment: 2 372tracksRegLiveness: true 373registers: [] 374liveins: 375 - { reg: '$r0', virtual-reg: '' } 376 - { reg: '$r2', virtual-reg: '' } 377frameInfo: 378 stackSize: 8 379 offsetAdjustment: 0 380 maxAlignment: 8 381fixedStack: 382 - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, 383 isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, 384 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 385stack: 386 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 387 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 388 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 389 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 390 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 391 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 392callSites: [] 393constants: [] 394machineFunctionInfo: {} 395body: | 396 ; CHECK-LABEL: name: invariant_add_use_reduce 397 ; CHECK: bb.0.entry: 398 ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.1(0x50000000) 399 ; CHECK-NEXT: liveins: $lr, $r0, $r2, $r7 400 ; CHECK-NEXT: {{ $}} 401 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 402 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 403 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 404 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 405 ; CHECK-NEXT: tCBZ $r2, %bb.4 406 ; CHECK-NEXT: {{ $}} 407 ; CHECK-NEXT: bb.1.vector.ph: 408 ; CHECK-NEXT: successors: %bb.2(0x80000000) 409 ; CHECK-NEXT: liveins: $r0, $r2 410 ; CHECK-NEXT: {{ $}} 411 ; CHECK-NEXT: renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 412 ; CHECK-NEXT: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 413 ; CHECK-NEXT: renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg 414 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 415 ; CHECK-NEXT: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg 416 ; CHECK-NEXT: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 417 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) 418 ; CHECK-NEXT: dead $lr = t2DLS renamable $r3 419 ; CHECK-NEXT: $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg 420 ; CHECK-NEXT: {{ $}} 421 ; CHECK-NEXT: bb.2.vector.body: 422 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 423 ; CHECK-NEXT: liveins: $q0, $r0, $r1, $r2 424 ; CHECK-NEXT: {{ $}} 425 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 426 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 427 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 428 ; CHECK-NEXT: $lr = tMOVr $r1, 14 /* CC::al */, $noreg 429 ; CHECK-NEXT: renamable $q1 = nsw MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 430 ; CHECK-NEXT: renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg 431 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 432 ; CHECK-NEXT: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg 433 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 434 ; CHECK-NEXT: {{ $}} 435 ; CHECK-NEXT: bb.3.exit: 436 ; CHECK-NEXT: liveins: $r12 437 ; CHECK-NEXT: {{ $}} 438 ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 439 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 440 ; CHECK-NEXT: {{ $}} 441 ; CHECK-NEXT: bb.4: 442 ; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 443 ; CHECK-NEXT: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 444 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 445 bb.0.entry: 446 successors: %bb.4(0x30000000), %bb.1(0x50000000) 447 liveins: $r0, $r2, $r7, $lr 448 449 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 450 frame-setup CFI_INSTRUCTION def_cfa_offset 8 451 frame-setup CFI_INSTRUCTION offset $lr, -4 452 frame-setup CFI_INSTRUCTION offset $r7, -8 453 tCBZ $r2, %bb.4 454 455 bb.1.vector.ph: 456 successors: %bb.2(0x80000000) 457 liveins: $r0, $r2 458 459 renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 460 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 461 renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg 462 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 463 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg 464 renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg 465 renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8) 466 $lr = t2DoLoopStart renamable $r3 467 $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg 468 469 bb.2.vector.body: 470 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 471 liveins: $q0, $r0, $r1, $r2 472 473 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 474 MVE_VPST 8, implicit $vpr 475 renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 476 $lr = tMOVr $r1, 14 /* CC::al */, $noreg 477 renamable $q1 = nsw MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 478 renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg 479 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 480 renamable $r12 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg 481 renamable $lr = t2LoopDec killed renamable $lr, 1 482 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 483 tB %bb.3, 14 /* CC::al */, $noreg 484 485 bb.3.exit: 486 liveins: $r12 487 488 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 489 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 490 491 bb.4: 492 renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 493 $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg 494 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 495 496... 497