1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s 3--- | 4 define dso_local void @incorrect_sub_16(ptr noalias nocapture %A, ptr noalias nocapture readonly %B, ptr noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 { 5 entry: 6 %cmp8 = icmp sgt i32 %N, 0 7 %0 = add i32 %N, 3 8 %1 = lshr i32 %0, 2 9 %2 = shl nuw i32 %1, 2 10 %3 = add i32 %2, -4 11 %4 = lshr i32 %3, 2 12 %5 = add nuw nsw i32 %4, 1 13 br i1 %cmp8, label %vector.ph, label %for.cond.cleanup 14 15 vector.ph: ; preds = %entry 16 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 17 br label %vector.body 18 19 vector.body: ; preds = %vector.body, %vector.ph 20 %lsr.iv17 = phi ptr [ %scevgep18, %vector.body ], [ %A, %vector.ph ] 21 %lsr.iv14 = phi ptr [ %scevgep15, %vector.body ], [ %C, %vector.ph ] 22 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %B, %vector.ph ] 23 %6 = phi i32 [ %start, %vector.ph ], [ %11, %vector.body ] 24 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ] 25 %lsr.iv13 = bitcast ptr %lsr.iv to ptr 26 %lsr.iv1416 = bitcast ptr %lsr.iv14 to ptr 27 %lsr.iv1719 = bitcast ptr %lsr.iv17 to ptr 28 %8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %7) 29 %9 = sub i32 %7, 7 30 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %lsr.iv13, i32 4, <8 x i1> %8, <8 x i16> undef) 31 %wide.masked.load12 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %lsr.iv1416, i32 4, <8 x i1> %8, <8 x i16> undef) 32 %10 = add nsw <8 x i16> %wide.masked.load12, %wide.masked.load 33 call void @llvm.masked.store.v8i16.p0(<8 x i16> %10, ptr %lsr.iv1719, i32 4, <8 x i1> %8) 34 %scevgep = getelementptr i16, ptr %lsr.iv, i32 8 35 %scevgep15 = getelementptr i16, ptr %lsr.iv14, i32 8 36 %scevgep18 = getelementptr i16, ptr %lsr.iv17, i32 8 37 %11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 38 %12 = icmp ne i32 %11, 0 39 br i1 %12, label %vector.body, label %for.cond.cleanup 40 41 for.cond.cleanup: ; preds = %vector.body, %entry 42 ret void 43 } 44 declare i32 @llvm.start.loop.iterations.i32(i32) 45 declare <8 x i1> @llvm.arm.mve.vctp16(i32) 46 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 47 declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>) 48 declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32 immarg, <8 x i1>) 49... 50--- 51name: incorrect_sub_16 52alignment: 2 53exposesReturnsTwice: false 54legalized: false 55regBankSelected: false 56selected: false 57failedISel: false 58tracksRegLiveness: true 59hasWinCFI: false 60registers: [] 61liveins: 62 - { reg: '$r0', virtual-reg: '' } 63 - { reg: '$r1', virtual-reg: '' } 64 - { reg: '$r2', virtual-reg: '' } 65 - { reg: '$r3', virtual-reg: '' } 66frameInfo: 67 isFrameAddressTaken: false 68 isReturnAddressTaken: false 69 hasStackMap: false 70 hasPatchPoint: false 71 stackSize: 8 72 offsetAdjustment: 0 73 maxAlignment: 4 74 adjustsStack: false 75 hasCalls: false 76 stackProtector: '' 77 maxCallFrameSize: 0 78 cvBytesOfCalleeSavedRegisters: 0 79 hasOpaqueSPAdjustment: false 80 hasVAStart: false 81 hasMustTailInVarArgFunc: false 82 localFrameSize: 0 83 savePoint: '' 84 restorePoint: '' 85fixedStack: [] 86stack: 87 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 88 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 89 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 90 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 91 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 92 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 93callSites: [] 94constants: [] 95machineFunctionInfo: {} 96body: | 97 ; CHECK-LABEL: name: incorrect_sub_16 98 ; CHECK: bb.0.entry: 99 ; CHECK-NEXT: successors: %bb.1(0x80000000) 100 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 101 ; CHECK-NEXT: {{ $}} 102 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 103 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 104 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 105 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 106 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 107 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 108 ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 109 ; CHECK-NEXT: {{ $}} 110 ; CHECK-NEXT: bb.1.vector.ph: 111 ; CHECK-NEXT: successors: %bb.2(0x80000000) 112 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 113 ; CHECK-NEXT: {{ $}} 114 ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 115 ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg 116 ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg 117 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg 118 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 119 ; CHECK-NEXT: {{ $}} 120 ; CHECK-NEXT: bb.2.vector.body: 121 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 122 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 123 ; CHECK-NEXT: {{ $}} 124 ; CHECK-NEXT: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg 125 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr 126 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) 127 ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) 128 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14 /* CC::al */, $noreg 129 ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 130 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 131 ; CHECK-NEXT: renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) 132 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 133 ; CHECK-NEXT: {{ $}} 134 ; CHECK-NEXT: bb.3.for.cond.cleanup: 135 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 136 bb.0.entry: 137 successors: %bb.1(0x80000000) 138 liveins: $r0, $r1, $r2, $r3, $r7, $lr 139 140 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 141 frame-setup CFI_INSTRUCTION def_cfa_offset 8 142 frame-setup CFI_INSTRUCTION offset $lr, -4 143 frame-setup CFI_INSTRUCTION offset $r7, -8 144 tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr 145 t2IT 11, 8, implicit-def $itstate 146 tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate 147 148 bb.1.vector.ph: 149 successors: %bb.2(0x80000000) 150 liveins: $r0, $r1, $r2, $r3, $r7, $lr 151 152 renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg 153 renamable $lr = t2MOVi 1, 14, $noreg, $noreg 154 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg 155 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 156 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg 157 $lr = t2DoLoopStart renamable $lr 158 159 bb.2.vector.body: 160 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 161 liveins: $lr, $r0, $r1, $r2, $r3 162 163 renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg 164 MVE_VPST 4, implicit $vpr 165 renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) 166 renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) 167 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14, $noreg 168 renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 169 MVE_VPST 8, implicit $vpr 170 renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) 171 renamable $lr = t2LoopDec killed renamable $lr, 1 172 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 173 tB %bb.3, 14, $noreg 174 175 bb.3.for.cond.cleanup: 176 tPOP_RET 14, $noreg, def $r7, def $pc 177 178... 179