1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s 3 4# Test that the scalar register that aliases a Q reg prevents the tail 5# predication. 6 7--- | 8 define dso_local i32 @no_vpsel_liveout(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %N) local_unnamed_addr #0 { 9 entry: 10 %cmp9 = icmp eq i32 %N, 0 11 %tmp = add i32 %N, 3 12 %tmp1 = lshr i32 %tmp, 2 13 %tmp2 = shl nuw i32 %tmp1, 2 14 %tmp3 = add i32 %tmp2, -4 15 %tmp4 = lshr i32 %tmp3, 2 16 %tmp5 = add nuw nsw i32 %tmp4, 1 17 br i1 %cmp9, label %for.cond.cleanup, label %vector.ph 18 19 vector.ph: ; preds = %entry 20 %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5) 21 br label %vector.body 22 23 vector.body: ; preds = %vector.body, %vector.ph 24 %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ] 25 %lsr.iv18 = phi ptr [ %scevgep19, %vector.body ], [ %b, %vector.ph ] 26 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %a, %vector.ph ] 27 %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp13, %vector.body ] 28 %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] 29 %lsr.iv17 = bitcast ptr %lsr.iv to ptr 30 %lsr.iv1820 = bitcast ptr %lsr.iv18 to ptr 31 %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) 32 %tmp9 = sub i32 %tmp7, 4 33 %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 34 %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> 35 %wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr %lsr.iv1820, i32 2, <4 x i1> %tmp8, <4 x i16> undef) 36 %tmp11 = sext <4 x i16> %wide.masked.load14 to <4 x i32> 37 %tmp12 = mul nsw <4 x i32> %tmp11, %tmp10 38 %tmp13 = add <4 x i32> %tmp12, %vec.phi 39 %scevgep = getelementptr i16, ptr %lsr.iv, i32 4 40 %scevgep19 = getelementptr i16, ptr %lsr.iv18, i32 4 41 %tmp14 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) 42 %tmp15 = icmp ne i32 %tmp14, 0 43 %lsr.iv.next = add nsw i32 %lsr.iv1, -1 44 br i1 %tmp15, label %vector.body, label %middle.block 45 46 middle.block: ; preds = %vector.body 47 %tmp16 = extractelement <4 x i32> %tmp13, i32 3 48 br label %for.cond.cleanup 49 50 for.cond.cleanup: ; preds = %middle.block, %entry 51 %res.0.lcssa = phi i32 [ 0, %entry ], [ %tmp16, %middle.block ] 52 ret i32 %res.0.lcssa 53 } 54 declare <4 x i16> @llvm.masked.load.v4i16.p0(ptr, i32 immarg, <4 x i1>, <4 x i16>) 55 declare i32 @llvm.start.loop.iterations.i32(i32) 56 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 57 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 58 59... 60--- 61name: no_vpsel_liveout 62alignment: 2 63exposesReturnsTwice: false 64legalized: false 65regBankSelected: false 66selected: false 67failedISel: false 68tracksRegLiveness: true 69hasWinCFI: false 70registers: [] 71liveins: 72 - { reg: '$r0', virtual-reg: '' } 73 - { reg: '$r1', virtual-reg: '' } 74 - { reg: '$r2', virtual-reg: '' } 75frameInfo: 76 isFrameAddressTaken: false 77 isReturnAddressTaken: false 78 hasStackMap: false 79 hasPatchPoint: false 80 stackSize: 8 81 offsetAdjustment: 0 82 maxAlignment: 4 83 adjustsStack: false 84 hasCalls: false 85 stackProtector: '' 86 maxCallFrameSize: 0 87 cvBytesOfCalleeSavedRegisters: 0 88 hasOpaqueSPAdjustment: false 89 hasVAStart: false 90 hasMustTailInVarArgFunc: false 91 localFrameSize: 0 92 savePoint: '' 93 restorePoint: '' 94fixedStack: [] 95stack: 96 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 97 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 98 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 99 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 100 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 101 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 102callSites: [] 103constants: [] 104machineFunctionInfo: {} 105body: | 106 ; CHECK-LABEL: name: no_vpsel_liveout 107 ; CHECK: bb.0.entry: 108 ; CHECK-NEXT: successors: %bb.1(0x80000000) 109 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 110 ; CHECK-NEXT: {{ $}} 111 ; CHECK-NEXT: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 112 ; CHECK-NEXT: t2IT 0, 4, implicit-def $itstate 113 ; CHECK-NEXT: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate 114 ; CHECK-NEXT: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate 115 ; CHECK-NEXT: {{ $}} 116 ; CHECK-NEXT: bb.1.vector.ph: 117 ; CHECK-NEXT: successors: %bb.2(0x80000000) 118 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 119 ; CHECK-NEXT: {{ $}} 120 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 121 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 122 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 123 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 124 ; CHECK-NEXT: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 125 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r2 126 ; CHECK-NEXT: {{ $}} 127 ; CHECK-NEXT: bb.2.vector.body: 128 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 129 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1 130 ; CHECK-NEXT: {{ $}} 131 ; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 132 ; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) 133 ; CHECK-NEXT: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 134 ; CHECK-NEXT: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 135 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.2 136 ; CHECK-NEXT: {{ $}} 137 ; CHECK-NEXT: bb.3.middle.block: 138 ; CHECK-NEXT: liveins: $q0 139 ; CHECK-NEXT: {{ $}} 140 ; CHECK-NEXT: $r0 = VMOVRS killed $s3, 14 /* CC::al */, $noreg, implicit killed $q0 141 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 142 bb.0.entry: 143 successors: %bb.1(0x80000000) 144 liveins: $r0, $r1, $r2, $lr, $r7 145 146 tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr 147 t2IT 0, 4, implicit-def $itstate 148 renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate 149 tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate 150 151 bb.1.vector.ph: 152 successors: %bb.2(0x80000000) 153 liveins: $r0, $r1, $r2, $lr, $r7 154 155 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 156 frame-setup CFI_INSTRUCTION def_cfa_offset 8 157 frame-setup CFI_INSTRUCTION offset $lr, -4 158 frame-setup CFI_INSTRUCTION offset $r7, -8 159 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg 160 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 161 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg 162 renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg 163 renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg 164 renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg 165 $lr = t2DoLoopStart renamable $r12 166 $r3 = tMOVr killed $r12, 14, $noreg 167 168 bb.2.vector.body: 169 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 170 liveins: $q0, $r0, $r1, $r2, $r3 171 172 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg 173 MVE_VPST 4, implicit $vpr 174 renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) 175 renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) 176 $lr = tMOVr $r3, 14, $noreg 177 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1 178 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg 179 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 180 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0 181 renamable $lr = t2LoopDec killed renamable $lr, 1 182 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 183 tB %bb.3, 14, $noreg 184 185 bb.3.middle.block: 186 liveins: $q0 187 188 $r0 = VMOVRS killed $s3, 14, $noreg, implicit $q0 189 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 190 191... 192