1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s 3 4--- | 5 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 6 target triple = "thumbv8.1m.main" 7 8 define void @size_limit(ptr nocapture %a, ptr nocapture readonly %b, ptr nocapture readonly %c, i32 %N) { 9 entry: 10 %start = call i32 @llvm.start.loop.iterations.i32(i32 %N) 11 %scevgep = getelementptr i32, ptr %a, i32 -1 12 %scevgep4 = getelementptr i32, ptr %c, i32 -1 13 %scevgep8 = getelementptr i32, ptr %b, i32 -1 14 br label %for.header 15 16 for.body: ; preds = %for.header 17 %scevgep11 = getelementptr i32, ptr %lsr.iv9, i32 1 18 %ld1 = load i32, ptr %scevgep11, align 4 19 %scevgep7 = getelementptr i32, ptr %lsr.iv5, i32 1 20 %ld2 = load i32, ptr %scevgep7, align 4 21 %mul = mul nsw i32 %ld2, %ld1 22 %scevgep3 = getelementptr i32, ptr %lsr.iv1, i32 1 23 store i32 %mul, ptr %scevgep3, align 4 24 %scevgep2 = getelementptr i32, ptr %lsr.iv1, i32 1 25 %scevgep6 = getelementptr i32, ptr %lsr.iv5, i32 1 26 %scevgep10 = getelementptr i32, ptr %lsr.iv9, i32 1 27 %count.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1) 28 %cmp = icmp ne i32 %count.next, 0 29 br i1 %cmp, label %for.header, label %for.cond.cleanup 30 31 for.cond.cleanup: ; preds = %for.body 32 ret void 33 34 for.header: ; preds = %for.body, %entry 35 %lsr.iv9 = phi ptr [ %scevgep8, %entry ], [ %scevgep10, %for.body ] 36 %lsr.iv5 = phi ptr [ %scevgep4, %entry ], [ %scevgep6, %for.body ] 37 %lsr.iv1 = phi ptr [ %scevgep, %entry ], [ %scevgep2, %for.body ] 38 %count = phi i32 [ %start, %entry ], [ %count.next, %for.body ] 39 br label %for.body 40 } 41 42 declare i32 @llvm.arm.space(i32 immarg, i32) #0 43 44 declare i32 @llvm.start.loop.iterations.i32(i32) #1 45 46 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 47 48 attributes #0 = { nounwind } 49 attributes #1 = { noduplicate nounwind } 50 51... 52--- 53name: size_limit 54alignment: 2 55exposesReturnsTwice: false 56legalized: false 57regBankSelected: false 58selected: false 59failedISel: false 60tracksRegLiveness: true 61hasWinCFI: false 62registers: [] 63liveins: 64 - { reg: '$r0', virtual-reg: '' } 65 - { reg: '$r1', virtual-reg: '' } 66 - { reg: '$r2', virtual-reg: '' } 67 - { reg: '$r3', virtual-reg: '' } 68frameInfo: 69 isFrameAddressTaken: false 70 isReturnAddressTaken: false 71 hasStackMap: false 72 hasPatchPoint: false 73 stackSize: 40 74 offsetAdjustment: 0 75 maxAlignment: 4 76 adjustsStack: false 77 hasCalls: false 78 stackProtector: '' 79 maxCallFrameSize: 0 80 cvBytesOfCalleeSavedRegisters: 0 81 hasOpaqueSPAdjustment: false 82 hasVAStart: false 83 hasMustTailInVarArgFunc: false 84 localFrameSize: 0 85 savePoint: '' 86 restorePoint: '' 87fixedStack: [] 88stack: 89 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 90 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 91 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 92 - { id: 1, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 93 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 94 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 95 - { id: 2, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, 96 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 97 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 98 - { id: 3, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, 99 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 100 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 101 - { id: 4, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4, 102 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 103 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 104 - { id: 5, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, 105 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 106 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 107 - { id: 6, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4, 108 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 109 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 110 - { id: 7, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4, 111 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 112 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 113 - { id: 8, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 114 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 115 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 116 - { id: 9, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 117 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 118 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 119callSites: [] 120constants: [] 121machineFunctionInfo: {} 122body: | 123 ; CHECK-LABEL: name: size_limit 124 ; CHECK: bb.0.entry: 125 ; CHECK-NEXT: successors: %bb.3(0x80000000) 126 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 127 ; CHECK-NEXT: {{ $}} 128 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 129 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 130 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 131 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 132 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 8, 14 /* CC::al */, $noreg 133 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 40 134 ; CHECK-NEXT: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg 135 ; CHECK-NEXT: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg 136 ; CHECK-NEXT: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 137 ; CHECK-NEXT: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 138 ; CHECK-NEXT: tSTRspi killed $r1, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) 139 ; CHECK-NEXT: tSTRspi killed $r2, $sp, 6, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1) 140 ; CHECK-NEXT: tSTRspi killed $r0, $sp, 5, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2) 141 ; CHECK-NEXT: tSTRspi killed $r3, $sp, 4, 14 /* CC::al */, $noreg :: (store (s32) into %stack.3) 142 ; CHECK-NEXT: tB %bb.3, 14 /* CC::al */, $noreg 143 ; CHECK-NEXT: {{ $}} 144 ; CHECK-NEXT: bb.1.for.body: 145 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) 146 ; CHECK-NEXT: {{ $}} 147 ; CHECK-NEXT: $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg :: (load (s32) from %stack.4) 148 ; CHECK-NEXT: renamable $r1, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep11) 149 ; CHECK-NEXT: $r2 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %stack.5) 150 ; CHECK-NEXT: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) 151 ; CHECK-NEXT: renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14 /* CC::al */, $noreg 152 ; CHECK-NEXT: $r3 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg :: (load (s32) from %stack.6) 153 ; CHECK-NEXT: early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, killed renamable $r3, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep3) 154 ; CHECK-NEXT: $r1 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.7) 155 ; CHECK-NEXT: $lr = tMOVr killed $r1, 14 /* CC::al */, $noreg 156 ; CHECK-NEXT: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr 157 ; CHECK-NEXT: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg 158 ; CHECK-NEXT: tSTRspi killed $r0, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) 159 ; CHECK-NEXT: tSTRspi killed $r2, $sp, 6, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1) 160 ; CHECK-NEXT: tSTRspi killed $r3, $sp, 5, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2) 161 ; CHECK-NEXT: t2STRi12 killed $r12, $sp, 16, 14 /* CC::al */, $noreg :: (store (s32) into %stack.3) 162 ; CHECK-NEXT: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr 163 ; CHECK-NEXT: tB %bb.2, 14 /* CC::al */, $noreg 164 ; CHECK-NEXT: {{ $}} 165 ; CHECK-NEXT: bb.2.for.cond.cleanup: 166 ; CHECK-NEXT: $sp = tADDspi $sp, 8, 14 /* CC::al */, $noreg 167 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 168 ; CHECK-NEXT: {{ $}} 169 ; CHECK-NEXT: bb.3.for.header: 170 ; CHECK-NEXT: successors: %bb.1(0x80000000) 171 ; CHECK-NEXT: {{ $}} 172 ; CHECK-NEXT: $r0 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %stack.3) 173 ; CHECK-NEXT: $r1 = tLDRspi $sp, 5, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2) 174 ; CHECK-NEXT: $r2 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1) 175 ; CHECK-NEXT: $r3 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 176 ; CHECK-NEXT: tSTRspi killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.7) 177 ; CHECK-NEXT: tSTRspi killed $r1, $sp, 1, 14 /* CC::al */, $noreg :: (store (s32) into %stack.6) 178 ; CHECK-NEXT: tSTRspi killed $r2, $sp, 2, 14 /* CC::al */, $noreg :: (store (s32) into %stack.5) 179 ; CHECK-NEXT: tSTRspi killed $r3, $sp, 3, 14 /* CC::al */, $noreg :: (store (s32) into %stack.4) 180 ; CHECK-NEXT: tB %bb.1, 14 /* CC::al */, $noreg 181 bb.0.entry: 182 successors: %bb.3(0x80000000) 183 liveins: $r0, $r1, $r2, $r3, $r7, $lr 184 185 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 186 frame-setup CFI_INSTRUCTION def_cfa_offset 8 187 frame-setup CFI_INSTRUCTION offset $lr, -4 188 frame-setup CFI_INSTRUCTION offset $r7, -8 189 $sp = frame-setup tSUBspi $sp, 8, 14, $noreg 190 frame-setup CFI_INSTRUCTION def_cfa_offset 40 191 $lr = t2DoLoopStart renamable $r3 192 renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg 193 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg 194 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg 195 tSTRspi killed $r1, $sp, 7, 14, $noreg :: (store (s32) into %stack.0) 196 tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store (s32) into %stack.1) 197 tSTRspi killed $r0, $sp, 5, 14, $noreg :: (store (s32) into %stack.2) 198 tSTRspi killed $r3, $sp, 4, 14, $noreg :: (store (s32) into %stack.3) 199 tB %bb.3, 14, $noreg 200 201 bb.1.for.body: 202 successors: %bb.3(0x40000000), %bb.2(0x40000000) 203 204 $r0 = tLDRspi $sp, 3, 14, $noreg :: (load (s32) from %stack.4) 205 renamable $r1, renamable $r0 = t2LDR_PRE renamable $r0, 4, 14, $noreg :: (load (s32) from %ir.scevgep11) 206 $r2 = tLDRspi $sp, 2, 14, $noreg :: (load (s32) from %stack.5) 207 renamable $r3, renamable $r2 = t2LDR_PRE renamable $r2, 4, 14, $noreg :: (load (s32) from %ir.scevgep7) 208 renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14, $noreg 209 $r3 = tLDRspi $sp, 1, 14, $noreg :: (load (s32) from %stack.6) 210 early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, renamable $r3, 4, 14, $noreg :: (store (s32) into %ir.scevgep3) 211 $r1 = tLDRspi $sp, 0, 14, $noreg :: (load (s32) from %stack.7) 212 $lr = tMOVr killed $r1, 14, $noreg 213 renamable $lr = t2LoopDec killed renamable $lr, 1 214 $r12 = tMOVr $lr, 14, $noreg 215 tSTRspi killed $r0, $sp, 7, 14, $noreg :: (store (s32) into %stack.0) 216 tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store (s32) into %stack.1) 217 tSTRspi killed $r3, $sp, 5, 14, $noreg :: (store (s32) into %stack.2) 218 t2STRi12 killed $r12, $sp, 16, 14, $noreg :: (store (s32) into %stack.3) 219 t2LoopEnd killed renamable $lr, %bb.3, implicit-def dead $cpsr 220 tB %bb.2, 14, $noreg 221 222 bb.2.for.cond.cleanup: 223 $sp = tADDspi $sp, 8, 14, $noreg 224 tPOP_RET 14, $noreg, def $r7, def $pc 225 226 bb.3.for.header: 227 successors: %bb.1(0x80000000) 228 229 $r0 = tLDRspi $sp, 4, 14, $noreg :: (load (s32) from %stack.3) 230 $r1 = tLDRspi $sp, 5, 14, $noreg :: (load (s32) from %stack.2) 231 $r2 = tLDRspi $sp, 6, 14, $noreg :: (load (s32) from %stack.1) 232 $r3 = tLDRspi $sp, 7, 14, $noreg :: (load (s32) from %stack.0) 233 tSTRspi killed $r0, $sp, 0, 14, $noreg :: (store (s32) into %stack.7) 234 tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store (s32) into %stack.6) 235 tSTRspi killed $r2, $sp, 2, 14, $noreg :: (store (s32) into %stack.5) 236 tSTRspi killed $r3, $sp, 3, 14, $noreg :: (store (s32) into %stack.4) 237 tB %bb.1, 14, $noreg 238 239... 240