1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve,+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s 3 4# There are 2 SUBS, so don't use tail predication 5 6--- | 7 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 8 target triple = "thumbv8.1m.main-arm-unknown-eabi" 9 10 define dso_local void @use_before_def(ptr noalias nocapture %A, ptr noalias nocapture readonly %B, ptr noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 { 11 entry: 12 %cmp8 = icmp sgt i32 %N, 0 13 %0 = add i32 %N, 3 14 %1 = lshr i32 %0, 2 15 %2 = shl nuw i32 %1, 2 16 %3 = add i32 %2, -4 17 %4 = lshr i32 %3, 2 18 %5 = add nuw nsw i32 %4, 1 19 br i1 %cmp8, label %vector.ph, label %for.cond.cleanup 20 21 vector.ph: ; preds = %entry 22 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 23 br label %vector.body 24 25 vector.body: ; preds = %vector.body, %vector.ph 26 %lsr.iv17 = phi ptr [ %scevgep18, %vector.body ], [ %A, %vector.ph ] 27 %lsr.iv14 = phi ptr [ %scevgep15, %vector.body ], [ %C, %vector.ph ] 28 %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %B, %vector.ph ] 29 %6 = phi i32 [ %start, %vector.ph ], [ %11, %vector.body ] 30 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ] 31 %lsr.iv13 = bitcast ptr %lsr.iv to ptr 32 %lsr.iv1416 = bitcast ptr %lsr.iv14 to ptr 33 %lsr.iv1719 = bitcast ptr %lsr.iv17 to ptr 34 %8 = call <4 x i1> @llvm.arm.vctp32(i32 %7) 35 %9 = sub i32 %7, 4 36 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv13, i32 4, <4 x i1> %8, <4 x i32> undef) 37 %wide.masked.load12 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1416, i32 4, <4 x i1> %8, <4 x i32> undef) 38 %10 = add nsw <4 x i32> %wide.masked.load12, %wide.masked.load 39 call void @llvm.masked.store.v4i32.p0(<4 x i32> %10, ptr %lsr.iv1719, i32 4, <4 x i1> %8) 40 %scevgep = getelementptr i32, ptr %lsr.iv, i32 4 41 %scevgep15 = getelementptr i32, ptr %lsr.iv14, i32 4 42 %scevgep18 = getelementptr i32, ptr %lsr.iv17, i32 4 43 %11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 44 %12 = icmp ne i32 %11, 0 45 br i1 %12, label %vector.body, label %for.cond.cleanup 46 47 for.cond.cleanup: ; preds = %vector.body, %entry 48 ret void 49 } 50 declare i32 @llvm.start.loop.iterations.i32(i32) 51 declare <4 x i1> @llvm.arm.vctp32(i32) 52 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 53 declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) 54 declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) 55 declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) 56 57... 58--- 59name: use_before_def 60alignment: 2 61exposesReturnsTwice: false 62legalized: false 63regBankSelected: false 64selected: false 65failedISel: false 66tracksRegLiveness: true 67hasWinCFI: false 68registers: [] 69liveins: 70 - { reg: '$r0', virtual-reg: '' } 71 - { reg: '$r1', virtual-reg: '' } 72 - { reg: '$r2', virtual-reg: '' } 73 - { reg: '$r3', virtual-reg: '' } 74frameInfo: 75 isFrameAddressTaken: false 76 isReturnAddressTaken: false 77 hasStackMap: false 78 hasPatchPoint: false 79 stackSize: 8 80 offsetAdjustment: 0 81 maxAlignment: 4 82 adjustsStack: false 83 hasCalls: false 84 stackProtector: '' 85 maxCallFrameSize: 0 86 cvBytesOfCalleeSavedRegisters: 0 87 hasOpaqueSPAdjustment: false 88 hasVAStart: false 89 hasMustTailInVarArgFunc: false 90 localFrameSize: 0 91 savePoint: '' 92 restorePoint: '' 93fixedStack: [] 94stack: 95 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 96 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 97 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 98 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 99 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 100 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 101callSites: [] 102constants: [] 103machineFunctionInfo: {} 104body: | 105 ; CHECK-LABEL: name: use_before_def 106 ; CHECK: bb.0.entry: 107 ; CHECK-NEXT: successors: %bb.1(0x80000000) 108 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3, $r7 109 ; CHECK-NEXT: {{ $}} 110 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 111 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 112 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 113 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 114 ; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 115 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7 116 ; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 117 ; CHECK-NEXT: t2IT 11, 8, implicit-def $itstate 118 ; CHECK-NEXT: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 119 ; CHECK-NEXT: {{ $}} 120 ; CHECK-NEXT: bb.1.vector.ph: 121 ; CHECK-NEXT: successors: %bb.2(0x80000000) 122 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3 123 ; CHECK-NEXT: {{ $}} 124 ; CHECK-NEXT: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 125 ; CHECK-NEXT: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg 126 ; CHECK-NEXT: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg 127 ; CHECK-NEXT: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg 128 ; CHECK-NEXT: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 129 ; CHECK-NEXT: {{ $}} 130 ; CHECK-NEXT: bb.2.vector.body: 131 ; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 132 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r3 133 ; CHECK-NEXT: {{ $}} 134 ; CHECK-NEXT: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg 135 ; CHECK-NEXT: MVE_VPST 4, implicit $vpr 136 ; CHECK-NEXT: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $lr :: (load (s128) from %ir.lsr.iv13, align 4) 137 ; CHECK-NEXT: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $lr :: (load (s128) from %ir.lsr.iv1416, align 4) 138 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg 139 ; CHECK-NEXT: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $lr, undef renamable $q0 140 ; CHECK-NEXT: MVE_VPST 8, implicit $vpr 141 ; CHECK-NEXT: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $lr :: (store (s128) into %ir.lsr.iv1719, align 4) 142 ; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg 143 ; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2 144 ; CHECK-NEXT: {{ $}} 145 ; CHECK-NEXT: bb.3.for.cond.cleanup: 146 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 147 bb.0.entry: 148 successors: %bb.1(0x80000000) 149 liveins: $r0, $r1, $r2, $r3, $r7, $lr 150 151 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 152 frame-setup CFI_INSTRUCTION def_cfa_offset 8 153 frame-setup CFI_INSTRUCTION offset $lr, -4 154 frame-setup CFI_INSTRUCTION offset $r7, -8 155 $r7 = frame-setup tMOVr $sp, 14, $noreg 156 frame-setup CFI_INSTRUCTION def_cfa_register $r7 157 tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr 158 t2IT 11, 8, implicit-def $itstate 159 tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate 160 161 bb.1.vector.ph: 162 successors: %bb.2(0x80000000) 163 liveins: $r0, $r1, $r2, $r3, $r7, $lr 164 165 renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg 166 renamable $lr = t2MOVi 1, 14, $noreg, $noreg 167 renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg 168 renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg 169 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg 170 $lr = t2DoLoopStart renamable $lr 171 172 bb.2.vector.body: 173 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 174 liveins: $lr, $r0, $r1, $r2, $r3 175 176 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg 177 MVE_VPST 4, implicit $vpr 178 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $lr :: (load (s128) from %ir.lsr.iv13, align 4) 179 renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $lr :: (load (s128) from %ir.lsr.iv1416, align 4) 180 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg 181 renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $lr, undef renamable $q0 182 MVE_VPST 8, implicit $vpr 183 renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $lr :: (store (s128) into %ir.lsr.iv1719, align 4) 184 renamable $lr = t2LoopDec killed renamable $lr, 1 185 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg 186 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 187 tB %bb.3, 14, $noreg 188 189 bb.3.for.cond.cleanup: 190 tPOP_RET 14, $noreg, def $r7, def $pc 191 192... 193