1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s 3 4--- | 5 define hidden arm_aapcs_vfpcc void @dont_ignore_vctp(ptr %pSrc, ptr %pDst, i32 %blockSize) local_unnamed_addr #0 { 6 entry: 7 %mul = shl i32 %blockSize, 1 8 %0 = add i32 %mul, 3 9 %1 = icmp slt i32 %mul, 4 10 %smin = select i1 %1, i32 %mul, i32 4 11 %2 = sub i32 %0, %smin 12 %3 = lshr i32 %2, 2 13 %4 = add nuw nsw i32 %3, 1 14 %start = call i32 @llvm.start.loop.iterations.i32(i32 %4) 15 br label %do.body 16 17 do.body: ; preds = %do.body, %entry 18 %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ] 19 %pDst.addr.0 = phi ptr [ %pDst, %entry ], [ %add.ptr4, %do.body ] 20 %pSrc.addr.0 = phi ptr [ %pSrc, %entry ], [ %add.ptr, %do.body ] 21 %5 = phi i32 [ %start, %entry ], [ %9, %do.body ] 22 %6 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0) 23 %7 = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %pSrc.addr.0, i32 4, <4 x i1> %6, <4 x float> undef) 24 %8 = fmul <4 x float> %7, <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00> 25 tail call void @llvm.masked.store.v4f32.p0(<4 x float> %8, ptr %pDst.addr.0, i32 4, <4 x i1> %6) 26 %add.ptr = getelementptr inbounds float, ptr %pSrc.addr.0, i32 4 27 %add.ptr4 = getelementptr inbounds float, ptr %pDst.addr.0, i32 4 28 %sub = add nsw i32 %blkCnt.0, -4 29 %9 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) 30 %10 = icmp ne i32 %9, 0 31 br i1 %10, label %do.body, label %do.end 32 33 do.end: ; preds = %do.body 34 ret void 35 } 36 declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1 37 declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32 immarg, <4 x i1>, <4 x float>) 38 declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32 immarg, <4 x i1>) 39 declare i32 @llvm.start.loop.iterations.i32(i32) 40 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 41 42... 43--- 44name: dont_ignore_vctp 45alignment: 16 46exposesReturnsTwice: false 47legalized: false 48regBankSelected: false 49selected: false 50failedISel: false 51tracksRegLiveness: true 52hasWinCFI: false 53registers: [] 54liveins: 55 - { reg: '$r0', virtual-reg: '' } 56 - { reg: '$r1', virtual-reg: '' } 57 - { reg: '$r2', virtual-reg: '' } 58frameInfo: 59 isFrameAddressTaken: false 60 isReturnAddressTaken: false 61 hasStackMap: false 62 hasPatchPoint: false 63 stackSize: 8 64 offsetAdjustment: 0 65 maxAlignment: 4 66 adjustsStack: false 67 hasCalls: false 68 stackProtector: '' 69 maxCallFrameSize: 0 70 cvBytesOfCalleeSavedRegisters: 0 71 hasOpaqueSPAdjustment: false 72 hasVAStart: false 73 hasMustTailInVarArgFunc: false 74 localFrameSize: 0 75 savePoint: '' 76 restorePoint: '' 77fixedStack: [] 78stack: 79 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 80 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 81 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 82 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 83 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 84 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 85callSites: [] 86constants: 87 - id: 0 88 value: '<4 x float> <float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00>' 89 alignment: 16 90 isTargetSpecific: false 91machineFunctionInfo: {} 92body: | 93 ; CHECK-LABEL: name: dont_ignore_vctp 94 ; CHECK: bb.0.entry: 95 ; CHECK-NEXT: successors: %bb.1(0x80000000) 96 ; CHECK-NEXT: liveins: $lr, $r0, $r1, $r2, $r7 97 ; CHECK-NEXT: {{ $}} 98 ; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 99 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8 100 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 101 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8 102 ; CHECK-NEXT: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg 103 ; CHECK-NEXT: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg 104 ; CHECK-NEXT: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) 105 ; CHECK-NEXT: $lr = MVE_DLSTP_32 killed renamable $r3 106 ; CHECK-NEXT: {{ $}} 107 ; CHECK-NEXT: bb.1.do.body (align 4): 108 ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000) 109 ; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1 110 ; CHECK-NEXT: {{ $}} 111 ; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg, $lr 112 ; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $lr, undef renamable $q1 113 ; CHECK-NEXT: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg, $lr 114 ; CHECK-NEXT: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg 115 ; CHECK-NEXT: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg 116 ; CHECK-NEXT: $lr = MVE_LETP killed renamable $lr, %bb.1 117 ; CHECK-NEXT: {{ $}} 118 ; CHECK-NEXT: bb.2.do.end: 119 ; CHECK-NEXT: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 120 ; CHECK-NEXT: {{ $}} 121 ; CHECK-NEXT: bb.3 (align 16): 122 ; CHECK-NEXT: CONSTPOOL_ENTRY 0, %const.0, 16 123 bb.0.entry: 124 successors: %bb.1(0x80000000) 125 liveins: $r0, $r1, $r2, $r7, $lr 126 127 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 128 frame-setup CFI_INSTRUCTION def_cfa_offset 8 129 frame-setup CFI_INSTRUCTION offset $lr, -4 130 frame-setup CFI_INSTRUCTION offset $r7, -8 131 renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg 132 renamable $r12 = t2MOVi 4, 14, $noreg, $noreg 133 tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr 134 t2IT 11, 8, implicit-def $itstate 135 $r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate 136 renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg 137 renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg 138 renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg 139 renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg 140 renamable $r2 = tLEApcrel %const.0, 14, $noreg 141 renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool) 142 $lr = t2DoLoopStart renamable $lr 143 144 bb.1.do.body (align 4): 145 successors: %bb.1(0x7c000000), %bb.2(0x04000000) 146 liveins: $lr, $q0, $r0, $r1, $r3 147 148 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $lr 149 MVE_VPST 2, implicit $vpr 150 renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $lr 151 renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, $lr, undef renamable $q1 152 MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr, $lr 153 renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg 154 renamable $lr = t2LoopDec killed renamable $lr, 1 155 renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg 156 renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg 157 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr 158 tB %bb.2, 14, $noreg 159 160 bb.2.do.end: 161 tPOP_RET 14, $noreg, def $r7, def $pc 162 163 bb.3 (align 16): 164 CONSTPOOL_ENTRY 0, %const.0, 16 165 166... 167