xref: /llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir (revision 59c6bd156cc8b42758ce90909615748e21c6eee2) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
3#
4--- |
5  @mask = external global i16
6  define dso_local void @test(ptr noalias nocapture %arg, ptr noalias nocapture readonly %arg1, i32 %arg2, ptr noalias nocapture readonly %arg3) local_unnamed_addr #0 {
7  bb:
8    %tmp = icmp eq i32 %arg2, 0
9    %tmp1 = add i32 %arg2, 3
10    %tmp2 = lshr i32 %tmp1, 2
11    %tmp3 = shl nuw i32 %tmp2, 2
12    %tmp4 = add i32 %tmp3, -4
13    %tmp5 = lshr i32 %tmp4, 2
14    %tmp6 = add nuw nsw i32 %tmp5, 1
15    %mask.gep9 = bitcast ptr @mask to ptr
16    %mask.load = load i16, ptr %mask.gep9
17    %conv.mask = zext i16 %mask.load to i32
18    %invariant.mask = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %conv.mask)
19    br i1 %tmp, label %bb27, label %bb3
20
21  bb3:                                              ; preds = %bb
22    %start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp6)
23    %scevgep1 = getelementptr i32, ptr %arg3, i32 -4
24    br label %bb9
25
26  bb9:                                              ; preds = %bb9, %bb3
27    %lsr.iv4 = phi ptr [ %scevgep6, %bb9 ], [ %scevgep1, %bb3 ]
28    %lsr.iv2 = phi ptr [ %scevgep3, %bb9 ], [ %arg1, %bb3 ]
29    %lsr.iv = phi ptr [ %scevgep, %bb9 ], [ %arg, %bb3 ]
30    %tmp7 = phi i32 [ %start, %bb3 ], [ %tmp12, %bb9 ]
31    %tmp8 = phi i32 [ %arg2, %bb3 ], [ %tmp11, %bb9 ]
32    %lsr.iv1 = bitcast ptr %lsr.iv to ptr
33    %lsr.iv24 = bitcast ptr %lsr.iv2 to ptr
34    %lsr.iv47 = bitcast ptr %lsr.iv4 to ptr
35    %vctp = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp8)
36    %and = and <4 x i1> %vctp, %invariant.mask
37    %tmp11 = sub i32 %tmp8, 4
38    %tmp17 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv24, i32 4, <4 x i1> %and, <4 x i32> undef)
39    %tmp22 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv1, i32 4, <4 x i1> %and, <4 x i32> undef)
40    %tmp23 = mul nsw <4 x i32> %tmp22, %tmp17
41    %scevgep2 = getelementptr <4 x i32>, ptr %lsr.iv47, i32 1
42    %load.limits = load <4 x i32>, ptr %scevgep2
43    %0 = insertelement <4 x i32> undef, i32 %conv.mask, i32 0
44    %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
45    %bad.icmp = icmp ule <4 x i32> %load.limits, %1
46    call void @llvm.masked.store.v4i32.p0(<4 x i32> %tmp23, ptr %lsr.iv1, i32 4, <4 x i1> %bad.icmp)
47    %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp7, i32 1)
48    %tmp13 = icmp ne i32 %tmp12, 0
49    %scevgep = getelementptr i32, ptr %lsr.iv, i32 4
50    %scevgep3 = getelementptr i32, ptr %lsr.iv2, i32 4
51    %scevgep6 = getelementptr i32, ptr %lsr.iv4, i32 4
52    br i1 %tmp13, label %bb9, label %bb27
53
54  bb27:                                             ; preds = %bb9, %bb
55    ret void
56  }
57  declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)
58  declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)
59  declare i32 @llvm.start.loop.iterations.i32(i32)
60  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
61  declare <4 x i1> @llvm.arm.mve.vctp32(i32)
62  declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
63
64...
65---
66name:            test
67alignment:       2
68exposesReturnsTwice: false
69legalized:       false
70regBankSelected: false
71selected:        false
72failedISel:      false
73tracksRegLiveness: true
74hasWinCFI:       false
75registers:       []
76liveins:
77  - { reg: '$r0', virtual-reg: '' }
78  - { reg: '$r1', virtual-reg: '' }
79  - { reg: '$r2', virtual-reg: '' }
80  - { reg: '$r3', virtual-reg: '' }
81frameInfo:
82  isFrameAddressTaken: false
83  isReturnAddressTaken: false
84  hasStackMap:     false
85  hasPatchPoint:   false
86  stackSize:       20
87  offsetAdjustment: 0
88  maxAlignment:    4
89  adjustsStack:    false
90  hasCalls:        false
91  stackProtector:  ''
92  maxCallFrameSize: 0
93  cvBytesOfCalleeSavedRegisters: 0
94  hasOpaqueSPAdjustment: false
95  hasVAStart:      false
96  hasMustTailInVarArgFunc: false
97  localFrameSize:  0
98  savePoint:       ''
99  restorePoint:    ''
100fixedStack:      []
101stack:
102  - { id: 0, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
103      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
104      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
105  - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
106      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
107      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
108  - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
109      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
110      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
111  - { id: 3, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
112      stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
113      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
114  - { id: 4, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
115      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
116      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
117callSites:       []
118constants:       []
119machineFunctionInfo: {}
120body:             |
121  ; CHECK-LABEL: name: test
122  ; CHECK: bb.0.bb:
123  ; CHECK-NEXT:   successors: %bb.3(0x30000000), %bb.1(0x50000000)
124  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7
125  ; CHECK-NEXT: {{  $}}
126  ; CHECK-NEXT:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
127  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 16
128  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -4
129  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r7, -8
130  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r5, -12
131  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r4, -16
132  ; CHECK-NEXT:   $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
133  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 20
134  ; CHECK-NEXT:   tCBZ $r2, %bb.3
135  ; CHECK-NEXT: {{  $}}
136  ; CHECK-NEXT: bb.1.bb3:
137  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
138  ; CHECK-NEXT:   liveins: $r0, $r1, $r2, $r3
139  ; CHECK-NEXT: {{  $}}
140  ; CHECK-NEXT:   $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14 /* CC::al */, $noreg
141  ; CHECK-NEXT:   renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
142  ; CHECK-NEXT:   $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14 /* CC::al */, $noreg
143  ; CHECK-NEXT:   renamable $r4 = t2BICri killed renamable $r4, 3, 14 /* CC::al */, $noreg, $noreg
144  ; CHECK-NEXT:   renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s16) from %ir.mask.gep9)
145  ; CHECK-NEXT:   renamable $r12 = t2SUBri killed renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg
146  ; CHECK-NEXT:   renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
147  ; CHECK-NEXT:   $vpr = VMSR_P0 $r5, 14 /* CC::al */, $noreg
148  ; CHECK-NEXT:   renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
149  ; CHECK-NEXT:   renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg
150  ; CHECK-NEXT:   VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
151  ; CHECK-NEXT:   renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, $noreg, undef renamable $q0
152  ; CHECK-NEXT:   $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
153  ; CHECK-NEXT: {{  $}}
154  ; CHECK-NEXT: bb.2.bb9:
155  ; CHECK-NEXT:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
156  ; CHECK-NEXT:   liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12
157  ; CHECK-NEXT: {{  $}}
158  ; CHECK-NEXT:   renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
159  ; CHECK-NEXT:   MVE_VPST 2, implicit $vpr
160  ; CHECK-NEXT:   renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
161  ; CHECK-NEXT:   renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)
162  ; CHECK-NEXT:   renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)
163  ; CHECK-NEXT:   renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
164  ; CHECK-NEXT:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
165  ; CHECK-NEXT:   renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep2, align 8)
166  ; CHECK-NEXT:   MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr
167  ; CHECK-NEXT:   MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
168  ; CHECK-NEXT:   $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
169  ; CHECK-NEXT:   $lr = t2LEUpdate killed renamable $lr, %bb.2
170  ; CHECK-NEXT: {{  $}}
171  ; CHECK-NEXT: bb.3.bb27:
172  ; CHECK-NEXT:   $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
173  ; CHECK-NEXT:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
174  bb.0.bb:
175    successors: %bb.3(0x30000000), %bb.1(0x50000000)
176    liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
177
178    frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
179    frame-setup CFI_INSTRUCTION def_cfa_offset 16
180    frame-setup CFI_INSTRUCTION offset $lr, -4
181    frame-setup CFI_INSTRUCTION offset $r7, -8
182    frame-setup CFI_INSTRUCTION offset $r5, -12
183    frame-setup CFI_INSTRUCTION offset $r4, -16
184    $sp = frame-setup tSUBspi $sp, 1, 14, $noreg
185    frame-setup CFI_INSTRUCTION def_cfa_offset 20
186    tCBZ $r2, %bb.3
187
188  bb.1.bb3:
189    successors: %bb.2(0x80000000)
190    liveins: $r0, $r1, $r2, $r3
191
192    $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14, $noreg
193    renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
194    $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14, $noreg
195    renamable $r4 = t2BICri killed renamable $r4, 3, 14, $noreg, $noreg
196    renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14, $noreg :: (dereferenceable load (s16) from %ir.mask.gep9)
197    renamable $r12 = t2SUBri killed renamable $r4, 4, 14, $noreg, $noreg
198    renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg
199    $vpr = VMSR_P0 $r5, 14, $noreg
200    renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14, $noreg, $noreg
201    renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg
202    VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0)
203    renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, $noreg, undef renamable $q0
204    $r3 = tMOVr $r0, 14, $noreg
205    $lr = t2DoLoopStart renamable $lr
206
207  bb.2.bb9:
208    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
209    liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12
210
211    renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0)
212    MVE_VPST 2, implicit $vpr
213    renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
214    renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)
215    renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)
216    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
217    renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
218    renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep2, align 8)
219    MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr
220    MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
221    renamable $lr = t2LoopDec killed renamable $lr, 1
222    $r0 = tMOVr $r3, 14, $noreg
223    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
224    tB %bb.3, 14, $noreg
225
226  bb.3.bb27:
227    $sp = tADDspi $sp, 1, 14, $noreg
228    tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc
229
230...
231