xref: /llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cmplx_cong.mir (revision 59c6bd156cc8b42758ce90909615748e21c6eee2) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
3
4--- |
5
6  @arm_cmplx_conj_f32_mve.cmplx_conj_sign = internal constant [4 x float] [float 1.000000e+00, float -1.000000e+00, float 1.000000e+00, float -1.000000e+00], align 4
7
8  define hidden void @arm_cmplx_conj_f32_mve(ptr %pSrc, ptr %pDst, i32 %blockSize) local_unnamed_addr #0 {
9  entry:
10    ret void
11  }
12
13...
14---
15name:            arm_cmplx_conj_f32_mve
16alignment:       4
17tracksRegLiveness: true
18registers:       []
19liveins:
20  - { reg: '$r0', virtual-reg: '' }
21  - { reg: '$r1', virtual-reg: '' }
22  - { reg: '$r2', virtual-reg: '' }
23frameInfo:
24  stackSize:       8
25  offsetAdjustment: 0
26  maxAlignment:    4
27fixedStack:      []
28stack:
29  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
30      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
31      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
33      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
34      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
35machineFunctionInfo: {}
36body:             |
37  ; CHECK-LABEL: name: arm_cmplx_conj_f32_mve
38  ; CHECK: bb.0:
39  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
40  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r2, $r4
41  ; CHECK-NEXT: {{  $}}
42  ; CHECK-NEXT:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
43  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
44  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -4
45  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r4, -8
46  ; CHECK-NEXT:   renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg
47  ; CHECK-NEXT:   $r4 = t2MOVi16 target-flags(arm-lo16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg
48  ; CHECK-NEXT:   $r4 = t2MOVTi16 killed $r4, target-flags(arm-hi16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg
49  ; CHECK-NEXT:   renamable $q0 = nnan ninf nsz MVE_VLDRWU32 killed renamable $r4, 0, 0, $noreg, $noreg
50  ; CHECK-NEXT:   $lr = MVE_DLSTP_32 killed renamable $r3
51  ; CHECK-NEXT: {{  $}}
52  ; CHECK-NEXT: bb.1 (align 4):
53  ; CHECK-NEXT:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
54  ; CHECK-NEXT:   liveins: $lr, $q0, $r0, $r1
55  ; CHECK-NEXT: {{  $}}
56  ; CHECK-NEXT:   renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg, $noreg
57  ; CHECK-NEXT:   renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
58  ; CHECK-NEXT:   MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg, $noreg
59  ; CHECK-NEXT:   renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
60  ; CHECK-NEXT:   renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
61  ; CHECK-NEXT:   $lr = MVE_LETP killed renamable $lr, %bb.1
62  ; CHECK-NEXT: {{  $}}
63  ; CHECK-NEXT: bb.2:
64  ; CHECK-NEXT:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
65  bb.0:
66    successors: %bb.1(0x80000000)
67    liveins: $r0, $r1, $r2, $r4, $lr
68
69    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
70    frame-setup CFI_INSTRUCTION def_cfa_offset 8
71    frame-setup CFI_INSTRUCTION offset $lr, -4
72    frame-setup CFI_INSTRUCTION offset $r4, -8
73    renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg
74    renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14 /* CC::al */, $noreg
75    tCMPi8 renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
76    t2IT 11, 8, implicit-def $itstate
77    $r12 = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
78    renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg
79    $r4 = t2MOVi16 target-flags(arm-lo16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg
80    renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg
81    renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
82    $r4 = t2MOVTi16 killed $r4, target-flags(arm-hi16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg
83    renamable $q0 = nnan ninf nsz MVE_VLDRWU32 killed renamable $r4, 0, 0, $noreg, $noreg
84    renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
85    $lr = t2DoLoopStart renamable $lr
86
87  bb.1 (align 4):
88    successors: %bb.1(0x7c000000), %bb.2(0x04000000)
89    liveins: $lr, $q0, $r0, $r1, $r3
90
91    renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
92    MVE_VPST 2, implicit $vpr
93    renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg
94    renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q1
95    MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr, $noreg
96    renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
97    renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
98    renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
99    renamable $lr = t2LoopDec killed renamable $lr, 1
100    t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
101    tB %bb.2, 14 /* CC::al */, $noreg
102
103  bb.2:
104    tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
105
106...
107