1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -mtriple=thumbv8.1m.main -mattr=+mve.fp -mve-tail-predication -tail-predication=enabled %s -S -o - | FileCheck %s 3 4define hidden i32 @_Z4loopPiPjiS0_i(ptr noalias nocapture readonly %s1, ptr noalias nocapture readonly %s2, i32 %x, ptr noalias nocapture %d, i32 %n) { 5; CHECK-LABEL: @_Z4loopPiPjiS0_i( 6; CHECK-NEXT: entry: 7; CHECK-NEXT: [[CMP63:%.*]] = icmp sgt i32 [[N:%.*]], 0 8; CHECK-NEXT: br i1 [[CMP63]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] 9; CHECK: for.body.lr.ph: 10; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[X:%.*]], 0 11; CHECK-NEXT: [[N_RND_UP77:%.*]] = add nuw i32 [[N]], 3 12; CHECK-NEXT: [[N_VEC79:%.*]] = and i32 [[N_RND_UP77]], -4 13; CHECK-NEXT: [[TRIP_COUNT_MINUS_183:%.*]] = add nsw i32 [[N]], -1 14; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N_VEC79]], -4 15; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[TMP0]], 2 16; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[TMP1]], 1 17; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP1]], 1 18; CHECK-NEXT: br i1 [[TOBOOL]], label [[VECTOR_BODY75_PREHEADER:%.*]], label [[VECTOR_PH:%.*]] 19; CHECK: vector.body75.preheader: 20; CHECK-NEXT: [[START1:%.*]] = call i32 @llvm.start.loop.iterations.i32(i32 [[TMP2]]) 21; CHECK-NEXT: br label [[VECTOR_BODY75:%.*]] 22; CHECK: vector.ph: 23; CHECK-NEXT: [[BROADCAST_SPLATINSERT71:%.*]] = insertelement <4 x i32> undef, i32 [[X]], i32 0 24; CHECK-NEXT: [[BROADCAST_SPLAT72:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT71]], <4 x i32> undef, <4 x i32> zeroinitializer 25; CHECK-NEXT: [[START2:%.*]] = call i32 @llvm.start.loop.iterations.i32(i32 [[TMP3]]) 26; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 27; CHECK: vector.body: 28; CHECK-NEXT: [[LSR_IV9:%.*]] = phi ptr [ [[SCEVGEP10:%.*]], [[VECTOR_BODY]] ], [ [[D:%.*]], [[VECTOR_PH]] ] 29; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 30; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ [[START2]], [[VECTOR_PH]] ], [ [[TMP10:%.*]], [[VECTOR_BODY]] ] 31; CHECK-NEXT: [[TMP5:%.*]] = phi i32 [ [[N]], [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ] 32; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> undef, i32 [[INDEX]], i32 0 33; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> undef, <4 x i32> zeroinitializer 34; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[BROADCAST_SPLAT]], <i32 0, i32 1, i32 2, i32 3> 35; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> undef, i32 [[TRIP_COUNT_MINUS_183]], i32 0 36; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> undef, <4 x i32> zeroinitializer 37; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i1> @llvm.arm.mve.vctp32(i32 [[TMP5]]) 38; CHECK-NEXT: [[TMP9]] = sub i32 [[TMP5]], 4 39; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[BROADCAST_SPLAT72]], ptr [[LSR_IV9]], i32 4, <4 x i1> [[TMP8]]) 40; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4 41; CHECK-NEXT: [[SCEVGEP10]] = getelementptr i32, ptr [[LSR_IV9]], i32 4 42; CHECK-NEXT: [[TMP10]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP4]], i32 1) 43; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 44; CHECK-NEXT: br i1 [[TMP11]], label [[VECTOR_BODY]], label [[FOR_COND_CLEANUP]] 45; CHECK: vector.body75: 46; CHECK-NEXT: [[LSR_IV6:%.*]] = phi ptr [ [[S1:%.*]], [[VECTOR_BODY75_PREHEADER]] ], [ [[SCEVGEP7:%.*]], [[VECTOR_BODY75]] ] 47; CHECK-NEXT: [[LSR_IV3:%.*]] = phi ptr [ [[S2:%.*]], [[VECTOR_BODY75_PREHEADER]] ], [ [[SCEVGEP4:%.*]], [[VECTOR_BODY75]] ] 48; CHECK-NEXT: [[LSR_IV:%.*]] = phi ptr [ [[D]], [[VECTOR_BODY75_PREHEADER]] ], [ [[SCEVGEP:%.*]], [[VECTOR_BODY75]] ] 49; CHECK-NEXT: [[INDEX80:%.*]] = phi i32 [ [[INDEX_NEXT81:%.*]], [[VECTOR_BODY75]] ], [ 0, [[VECTOR_BODY75_PREHEADER]] ] 50; CHECK-NEXT: [[TMP12:%.*]] = phi i32 [ [[START1]], [[VECTOR_BODY75_PREHEADER]] ], [ [[TMP17:%.*]], [[VECTOR_BODY75]] ] 51; CHECK-NEXT: [[BROADCAST_SPLATINSERT84:%.*]] = insertelement <4 x i32> undef, i32 [[INDEX80]], i32 0 52; CHECK-NEXT: [[BROADCAST_SPLAT85:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT84]], <4 x i32> undef, <4 x i32> zeroinitializer 53; CHECK-NEXT: [[INDUCTION86:%.*]] = add <4 x i32> [[BROADCAST_SPLAT85]], <i32 0, i32 1, i32 2, i32 3> 54; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> undef, i32 [[TRIP_COUNT_MINUS_183]], i32 0 55; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[TMP13]], <4 x i32> undef, <4 x i32> zeroinitializer 56; CHECK-NEXT: [[TMP15:%.*]] = icmp ule <4 x i32> [[INDUCTION86]], [[TMP14]] 57; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[LSR_IV6]], i32 4, <4 x i1> [[TMP15]], <4 x i32> undef) 58; CHECK-NEXT: [[WIDE_MASKED_LOAD89:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[LSR_IV3]], i32 4, <4 x i1> [[TMP15]], <4 x i32> undef) 59; CHECK-NEXT: [[TMP16:%.*]] = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> [[WIDE_MASKED_LOAD89]], <4 x i32> [[WIDE_MASKED_LOAD]]) 60; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0(<4 x i32> [[TMP16]], ptr [[LSR_IV]], i32 4, <4 x i1> [[TMP15]]) 61; CHECK-NEXT: [[INDEX_NEXT81]] = add i32 [[INDEX80]], 4 62; CHECK-NEXT: [[SCEVGEP]] = getelementptr i32, ptr [[LSR_IV]], i32 4 63; CHECK-NEXT: [[SCEVGEP4]] = getelementptr i32, ptr [[LSR_IV3]], i32 4 64; CHECK-NEXT: [[SCEVGEP7]] = getelementptr i32, ptr [[LSR_IV6]], i32 4 65; CHECK-NEXT: [[TMP17]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP12]], i32 1) 66; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 67; CHECK-NEXT: br i1 [[TMP18]], label [[VECTOR_BODY75]], label [[FOR_COND_CLEANUP]] 68; CHECK: for.cond.cleanup: 69; CHECK-NEXT: ret i32 0 70; 71entry: 72 %cmp63 = icmp sgt i32 %n, 0 73 br i1 %cmp63, label %for.body.lr.ph, label %for.cond.cleanup 74 75for.body.lr.ph: ; preds = %entry 76 %tobool = icmp eq i32 %x, 0 77 %n.rnd.up77 = add nuw i32 %n, 3 78 %n.vec79 = and i32 %n.rnd.up77, -4 79 %trip.count.minus.183 = add nsw i32 %n, -1 80 %0 = add i32 %n.vec79, -4 81 %1 = lshr i32 %0, 2 82 %2 = add nuw nsw i32 %1, 1 83 %3 = add nuw nsw i32 %1, 1 84 br i1 %tobool, label %vector.body75.preheader, label %vector.ph 85 86vector.body75.preheader: ; preds = %for.body.lr.ph 87 %start1 = call i32 @llvm.start.loop.iterations.i32(i32 %2) 88 br label %vector.body75 89 90vector.ph: ; preds = %for.body.lr.ph 91 %broadcast.splatinsert71 = insertelement <4 x i32> undef, i32 %x, i32 0 92 %broadcast.splat72 = shufflevector <4 x i32> %broadcast.splatinsert71, <4 x i32> undef, <4 x i32> zeroinitializer 93 %start2 = call i32 @llvm.start.loop.iterations.i32(i32 %3) 94 br label %vector.body 95 96vector.body: ; preds = %vector.body, %vector.ph 97 %lsr.iv9 = phi ptr [ %scevgep10, %vector.body ], [ %d, %vector.ph ] 98 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ] 99 %4 = phi i32 [ %start2, %vector.ph ], [ %8, %vector.body ] 100 %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0 101 %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 102 %induction = add <4 x i32> %broadcast.splat, <i32 0, i32 1, i32 2, i32 3> 103 %5 = insertelement <4 x i32> undef, i32 %trip.count.minus.183, i32 0 104 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <4 x i32> zeroinitializer 105 %7 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n) 106 call void @llvm.masked.store.v4i32.p0(<4 x i32> %broadcast.splat72, ptr %lsr.iv9, i32 4, <4 x i1> %7) 107 %index.next = add i32 %index, 4 108 %scevgep10 = getelementptr i32, ptr %lsr.iv9, i32 4 109 %8 = call i32 @llvm.loop.decrement.reg.i32(i32 %4, i32 1) 110 %9 = icmp ne i32 %8, 0 111 br i1 %9, label %vector.body, label %for.cond.cleanup 112 113vector.body75: ; preds = %vector.body75, %vector.body75.preheader 114 %lsr.iv6 = phi ptr [ %s1, %vector.body75.preheader ], [ %scevgep7, %vector.body75 ] 115 %lsr.iv3 = phi ptr [ %s2, %vector.body75.preheader ], [ %scevgep4, %vector.body75 ] 116 %lsr.iv = phi ptr [ %d, %vector.body75.preheader ], [ %scevgep, %vector.body75 ] 117 %index80 = phi i32 [ %index.next81, %vector.body75 ], [ 0, %vector.body75.preheader ] 118 %10 = phi i32 [ %start1, %vector.body75.preheader ], [ %15, %vector.body75 ] 119 %broadcast.splatinsert84 = insertelement <4 x i32> undef, i32 %index80, i32 0 120 %broadcast.splat85 = shufflevector <4 x i32> %broadcast.splatinsert84, <4 x i32> undef, <4 x i32> zeroinitializer 121 %induction86 = add <4 x i32> %broadcast.splat85, <i32 0, i32 1, i32 2, i32 3> 122 %11 = insertelement <4 x i32> undef, i32 %trip.count.minus.183, i32 0 123 %12 = shufflevector <4 x i32> %11, <4 x i32> undef, <4 x i32> zeroinitializer 124 %13 = icmp ule <4 x i32> %induction86, %12 125 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv6, i32 4, <4 x i1> %13, <4 x i32> undef) 126 %wide.masked.load89 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %lsr.iv3, i32 4, <4 x i1> %13, <4 x i32> undef) 127 %14 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %wide.masked.load89, <4 x i32> %wide.masked.load) 128 call void @llvm.masked.store.v4i32.p0(<4 x i32> %14, ptr %lsr.iv, i32 4, <4 x i1> %13) 129 %index.next81 = add i32 %index80, 4 130 %scevgep = getelementptr i32, ptr %lsr.iv, i32 4 131 %scevgep4 = getelementptr i32, ptr %lsr.iv3, i32 4 132 %scevgep7 = getelementptr i32, ptr %lsr.iv6, i32 4 133 %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %10, i32 1) 134 %16 = icmp ne i32 %15, 0 135 br i1 %16, label %vector.body75, label %for.cond.cleanup 136 137for.cond.cleanup: ; preds = %vector.body, %vector.body75, %entry 138 ret i32 0 139} 140declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>) 141declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>) 142declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) 143declare i32 @llvm.start.loop.iterations.i32(i32) 144declare i32 @llvm.loop.decrement.reg.i32(i32, i32) 145 146declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) 147declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32) 148declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32) 149