1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3 4--- | 5 %struct.arm_biquad_casd_df1_inst_q31 = type { ptr, ptr, i32, i32 } 6 7 define hidden void @arm_biquad_cascade_df1_q31(ptr nocapture readonly %arg, ptr nocapture readonly %arg1, ptr nocapture %arg2, i32 %arg3) #0 { 8 bb: 9 %i = bitcast ptr %arg to ptr 10 %i4 = load ptr, ptr %i, align 4 11 %i5 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_q31, ptr %arg, i32 0, i32 1 12 %i6 = load ptr, ptr %i5, align 4 13 %i7 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_q31, ptr %arg, i32 0, i32 2 14 %i8 = load i32, ptr %i7, align 4 15 %i9 = sub i32 31, %i8 16 %i10 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_q31, ptr %arg, i32 0, i32 3 17 %i11 = load i32, ptr %i10, align 4 18 br label %bb12 19 20 bb12: ; preds = %bb74, %bb 21 %i13 = phi ptr [ %i6, %bb ], [ %i18, %bb74 ] 22 %i14 = phi ptr [ %i4, %bb ], [ %i85, %bb74 ] 23 %i15 = phi ptr [ %arg1, %bb ], [ %arg2, %bb74 ] 24 %i16 = phi i32 [ %i11, %bb ], [ %i89, %bb74 ] 25 %i18 = getelementptr inbounds i32, ptr %i13, i32 5 26 %i19 = load i32, ptr %i14, align 4 27 %i20 = getelementptr inbounds i32, ptr %i14, i32 1 28 %i21 = load i32, ptr %i20, align 4 29 %i22 = getelementptr inbounds i32, ptr %i14, i32 2 30 %i23 = load i32, ptr %i22, align 4 31 %i24 = getelementptr inbounds i32, ptr %i14, i32 3 32 %i25 = load i32, ptr %i24, align 4 33 %i26 = call i1 @llvm.test.set.loop.iterations.i32(i32 %arg3) 34 br i1 %i26, label %bb27, label %bb74 35 36 bb27: ; preds = %bb12 37 %i28 = getelementptr inbounds i32, ptr %i13, i32 4 38 %i29 = load i32, ptr %i28, align 4 39 %i30 = getelementptr inbounds i32, ptr %i13, i32 3 40 %i31 = load i32, ptr %i30, align 4 41 %i32 = getelementptr inbounds i32, ptr %i13, i32 2 42 %i33 = load i32, ptr %i32, align 4 43 %i34 = getelementptr inbounds i32, ptr %i13, i32 1 44 %i35 = load i32, ptr %i34, align 4 45 %i36 = load i32, ptr %i13, align 4 46 br label %bb37 47 48 bb37: ; preds = %bb37, %bb27 49 %lsr.iv = phi i32 [ %lsr.iv.next, %bb37 ], [ %arg3, %bb27 ] 50 %i38 = phi ptr [ %i15, %bb27 ], [ %i51, %bb37 ] 51 %i39 = phi ptr [ %arg2, %bb27 ], [ %i69, %bb37 ] 52 %i40 = phi i32 [ %i25, %bb27 ], [ %i41, %bb37 ] 53 %i41 = phi i32 [ %i23, %bb27 ], [ %i68, %bb37 ] 54 %i42 = phi i32 [ %i21, %bb27 ], [ %i43, %bb37 ] 55 %i43 = phi i32 [ %i19, %bb27 ], [ %i52, %bb37 ] 56 %i45 = sext i32 %i29 to i64 57 %i46 = sext i32 %i31 to i64 58 %i47 = sext i32 %i33 to i64 59 %i48 = sext i32 %i35 to i64 60 %i49 = sext i32 %i36 to i64 61 %i50 = zext i32 %i9 to i64 62 %i51 = getelementptr inbounds i32, ptr %i38, i32 1 63 %i52 = load i32, ptr %i38, align 4 64 %i53 = sext i32 %i52 to i64 65 %i54 = mul nsw i64 %i53, %i49 66 %i55 = sext i32 %i43 to i64 67 %i56 = mul nsw i64 %i55, %i48 68 %i57 = sext i32 %i42 to i64 69 %i58 = mul nsw i64 %i57, %i47 70 %i59 = sext i32 %i41 to i64 71 %i60 = mul nsw i64 %i59, %i46 72 %i61 = sext i32 %i40 to i64 73 %i62 = mul nsw i64 %i61, %i45 74 %i63 = add i64 %i58, %i56 75 %i64 = add i64 %i63, %i60 76 %i65 = add i64 %i64, %i62 77 %i66 = add i64 %i65, %i54 78 %i67 = ashr i64 %i66, %i50 79 %i68 = trunc i64 %i67 to i32 80 %i69 = getelementptr inbounds i32, ptr %i39, i32 1 81 store i32 %i68, ptr %i39, align 4 82 %i70 = call i32 @llvm.loop.decrement.reg.i32(i32 %lsr.iv, i32 1) 83 %i71 = icmp ne i32 %i70, 0 84 %lsr.iv.next = add i32 %lsr.iv, -1 85 br i1 %i71, label %bb37, label %bb72 86 87 bb72: ; preds = %bb37 88 %i73 = trunc i64 %i67 to i32 89 br label %bb74 90 91 bb74: ; preds = %bb72, %bb12 92 %i75 = phi i32 [ %i19, %bb12 ], [ %i52, %bb72 ] 93 %i76 = phi i32 [ %i21, %bb12 ], [ %i43, %bb72 ] 94 %i77 = phi i32 [ %i23, %bb12 ], [ %i73, %bb72 ] 95 %i78 = phi i32 [ %i25, %bb12 ], [ %i41, %bb72 ] 96 store i32 %i75, ptr %i14, align 4 97 %i79 = bitcast ptr %i14 to ptr 98 %i80 = getelementptr inbounds i8, ptr %i79, i32 4 99 %i81 = bitcast ptr %i80 to ptr 100 store i32 %i76, ptr %i81, align 4 101 %i82 = bitcast ptr %i14 to ptr 102 %i83 = getelementptr inbounds i8, ptr %i82, i32 8 103 %i84 = bitcast ptr %i83 to ptr 104 store i32 %i77, ptr %i84, align 4 105 %i85 = getelementptr inbounds i32, ptr %i14, i32 4 106 %i86 = bitcast ptr %i14 to ptr 107 %i87 = getelementptr inbounds i8, ptr %i86, i32 12 108 %i88 = bitcast ptr %i87 to ptr 109 store i32 %i78, ptr %i88, align 4 110 %i89 = add i32 %i16, -1 111 %i90 = icmp eq i32 %i89, 0 112 br i1 %i90, label %bb91, label %bb12 113 114 bb91: ; preds = %bb74 115 ret void 116 } 117 118 declare i1 @llvm.test.set.loop.iterations.i32(i32) #1 119 120 declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #1 121 122 attributes #0 = { optsize "target-cpu"="cortex-m55" } 123 attributes #1 = { noduplicate nounwind "target-cpu"="cortex-m55" } 124 125... 126--- 127name: arm_biquad_cascade_df1_q31 128alignment: 2 129tracksRegLiveness: true 130registers: [] 131liveins: 132 - { reg: '$r0', virtual-reg: '' } 133 - { reg: '$r1', virtual-reg: '' } 134 - { reg: '$r2', virtual-reg: '' } 135 - { reg: '$r3', virtual-reg: '' } 136frameInfo: 137 stackSize: 76 138 offsetAdjustment: 0 139 maxAlignment: 4 140 localFrameSize: 0 141 savePoint: '' 142 restorePoint: '' 143fixedStack: [] 144stack: 145 - { id: 0, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4, 146 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 147 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 148 - { id: 1, name: '', type: spill-slot, offset: -44, size: 4, alignment: 4, 149 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 150 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 151 - { id: 2, name: '', type: spill-slot, offset: -48, size: 4, alignment: 4, 152 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 153 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 154 - { id: 3, name: '', type: spill-slot, offset: -52, size: 4, alignment: 4, 155 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 156 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 157 - { id: 4, name: '', type: spill-slot, offset: -56, size: 4, alignment: 4, 158 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 159 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 160 - { id: 5, name: '', type: spill-slot, offset: -60, size: 4, alignment: 4, 161 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 162 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 163 - { id: 6, name: '', type: spill-slot, offset: -64, size: 4, alignment: 4, 164 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 165 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 166 - { id: 7, name: '', type: spill-slot, offset: -68, size: 4, alignment: 4, 167 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 168 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 169 - { id: 8, name: '', type: spill-slot, offset: -72, size: 4, alignment: 4, 170 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 171 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 172 - { id: 9, name: '', type: spill-slot, offset: -76, size: 4, alignment: 4, 173 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 174 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 175 - { id: 10, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 176 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 177 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 178 - { id: 11, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 179 stack-id: default, callee-saved-register: '$r11', callee-saved-restored: true, 180 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 181 - { id: 12, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 182 stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true, 183 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 184 - { id: 13, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 185 stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true, 186 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 187 - { id: 14, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, 188 stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true, 189 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 190 - { id: 15, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, 191 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 192 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 193 - { id: 16, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4, 194 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, 195 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 196 - { id: 17, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, 197 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 198 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 199 - { id: 18, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4, 200 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 201 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 202callSites: [] 203constants: [] 204machineFunctionInfo: {} 205body: | 206 ; CHECK-LABEL: name: arm_biquad_cascade_df1_q31 207 ; CHECK: bb.0.bb: 208 ; CHECK-NEXT: successors: %bb.1(0x80000000) 209 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr 210 ; CHECK-NEXT: {{ $}} 211 ; CHECK-NEXT: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr 212 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 36 213 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4 214 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r11, -8 215 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r10, -12 216 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r9, -16 217 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r8, -20 218 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -24 219 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r6, -28 220 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r5, -32 221 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r4, -36 222 ; CHECK-NEXT: $sp = frame-setup tSUBspi $sp, 10, 14 /* CC::al */, $noreg 223 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 76 224 ; CHECK-NEXT: $r6, $r5 = t2LDRDi8 $r0, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i7), (load (s32) from %ir.i10) 225 ; CHECK-NEXT: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg 226 ; CHECK-NEXT: $r3, $r7 = t2LDRDi8 killed $r0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i), (load (s32) from %ir.i5) 227 ; CHECK-NEXT: renamable $r0 = t2RSBri killed renamable $r6, 31, 14 /* CC::al */, $noreg, $noreg 228 ; CHECK-NEXT: t2STMIA $sp, 14 /* CC::al */, $noreg, killed $r0, $r2, $r8 :: (store (s32) into %stack.9), (store (s32) into %stack.8), (store (s32) into %stack.7) 229 ; CHECK-NEXT: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg 230 ; CHECK-NEXT: renamable $r2 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.9) 231 ; CHECK-NEXT: {{ $}} 232 ; CHECK-NEXT: bb.1.bb12 (align 4): 233 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.5(0x40000000) 234 ; CHECK-NEXT: liveins: $r1, $r2, $r3, $r5, $r7, $r8, $r12 235 ; CHECK-NEXT: {{ $}} 236 ; CHECK-NEXT: $r9, $r4 = t2LDRDi8 $r3, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i14), (load (s32) from %ir.i20) 237 ; CHECK-NEXT: $r6, $r0 = t2LDRDi8 $r3, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i22), (load (s32) from %ir.i24) 238 ; CHECK-NEXT: dead $lr = t2WLS renamable $r8, %bb.5 239 ; CHECK-NEXT: {{ $}} 240 ; CHECK-NEXT: bb.2.bb27: 241 ; CHECK-NEXT: successors: %bb.3(0x80000000) 242 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12 243 ; CHECK-NEXT: {{ $}} 244 ; CHECK-NEXT: t2STRDi8 killed $r3, killed $r5, $sp, 12, 14 /* CC::al */, $noreg :: (store (s32) into %stack.6), (store (s32) into %stack.5) 245 ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r7, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i13) 246 ; CHECK-NEXT: tSTRspi killed renamable $r3, $sp, 9, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) 247 ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i34) 248 ; CHECK-NEXT: tSTRspi killed renamable $r3, $sp, 8, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1) 249 ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i32) 250 ; CHECK-NEXT: tSTRspi killed renamable $r3, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2) 251 ; CHECK-NEXT: renamable $r3 = tLDRi renamable $r7, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i30) 252 ; CHECK-NEXT: t2STRDi8 $r7, killed $r3, $sp, 20, 14 /* CC::al */, $noreg :: (store (s32) into %stack.4), (store (s32) into %stack.3) 253 ; CHECK-NEXT: renamable $r10 = t2LDRi12 killed renamable $r7, 16, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i28) 254 ; CHECK-NEXT: {{ $}} 255 ; CHECK-NEXT: bb.3.bb37 (align 4): 256 ; CHECK-NEXT: successors: %bb.3(0x7c000000), %bb.4(0x04000000) 257 ; CHECK-NEXT: liveins: $r0, $r1, $r2, $r4, $r6, $r8, $r9, $r10, $r12 258 ; CHECK-NEXT: {{ $}} 259 ; CHECK-NEXT: $r7 = tMOVr killed $r6, 14 /* CC::al */, $noreg 260 ; CHECK-NEXT: renamable $r6 = tLDRspi $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1) 261 ; CHECK-NEXT: renamable $r3 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2) 262 ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMULL $r9, killed renamable $r6, 14 /* CC::al */, $noreg 263 ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r4, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 264 ; CHECK-NEXT: renamable $r3 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load (s32) from %stack.3) 265 ; CHECK-NEXT: $r5 = tMOVr killed $r9, 14 /* CC::al */, $noreg 266 ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL renamable $r7, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 267 ; CHECK-NEXT: renamable $r9, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i38) 268 ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL killed renamable $r0, renamable $r10, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 269 ; CHECK-NEXT: renamable $r0 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 270 ; CHECK-NEXT: $lr = tMOVr $r8, 14 /* CC::al */, $noreg 271 ; CHECK-NEXT: renamable $r6, renamable $r11 = t2SMLAL renamable $r9, killed renamable $r0, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 272 ; CHECK-NEXT: early-clobber renamable $r6, dead early-clobber renamable $r11 = MVE_ASRLr killed renamable $r6, killed renamable $r11, renamable $r2, 14 /* CC::al */, $noreg 273 ; CHECK-NEXT: early-clobber renamable $r12 = t2STR_POST renamable $r6, killed renamable $r12, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i39) 274 ; CHECK-NEXT: renamable $r8 = t2SUBri killed renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg 275 ; CHECK-NEXT: $r0 = tMOVr $r7, 14 /* CC::al */, $noreg 276 ; CHECK-NEXT: $r4 = tMOVr $r5, 14 /* CC::al */, $noreg 277 ; CHECK-NEXT: dead $lr = t2LEUpdate killed renamable $lr, %bb.3 278 ; CHECK-NEXT: {{ $}} 279 ; CHECK-NEXT: bb.4.bb72: 280 ; CHECK-NEXT: successors: %bb.5(0x80000000) 281 ; CHECK-NEXT: liveins: $r2, $r5, $r6, $r7, $r9 282 ; CHECK-NEXT: {{ $}} 283 ; CHECK-NEXT: $r0 = tMOVr killed $r7, 14 /* CC::al */, $noreg 284 ; CHECK-NEXT: $r7 = tADDrSPi $sp, 3, 14 /* CC::al */, $noreg 285 ; CHECK-NEXT: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg 286 ; CHECK-NEXT: $r12, $r8 = t2LDRDi8 $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %stack.8), (load (s32) from %stack.7) 287 ; CHECK-NEXT: tLDMIA killed $r7, 14 /* CC::al */, $noreg, def $r3, def $r5, def $r7 :: (load (s32) from %stack.6), (load (s32) from %stack.5), (load (s32) from %stack.4) 288 ; CHECK-NEXT: {{ $}} 289 ; CHECK-NEXT: bb.5.bb74: 290 ; CHECK-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000) 291 ; CHECK-NEXT: liveins: $r0, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12, $r2 292 ; CHECK-NEXT: {{ $}} 293 ; CHECK-NEXT: renamable $r7, dead $cpsr = nuw tADDi8 killed renamable $r7, 20, 14 /* CC::al */, $noreg 294 ; CHECK-NEXT: t2STRDi8 killed $r9, killed $r4, $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i14), (store (s32) into %ir.i81) 295 ; CHECK-NEXT: t2STRDi8 killed $r6, killed $r0, $r3, 8, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i84), (store (s32) into %ir.i88) 296 ; CHECK-NEXT: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg 297 ; CHECK-NEXT: renamable $r5, $cpsr = tSUBi8 killed renamable $r5, 1, 14 /* CC::al */, $noreg 298 ; CHECK-NEXT: $r1 = tMOVr $r12, 14 /* CC::al */, $noreg 299 ; CHECK-NEXT: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr 300 ; CHECK-NEXT: {{ $}} 301 ; CHECK-NEXT: bb.6.bb91: 302 ; CHECK-NEXT: $sp = frame-destroy tADDspi $sp, 10, 14 /* CC::al */, $noreg 303 ; CHECK-NEXT: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc 304 bb.0.bb: 305 successors: %bb.1(0x80000000) 306 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr 307 308 $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr 309 frame-setup CFI_INSTRUCTION def_cfa_offset 36 310 frame-setup CFI_INSTRUCTION offset $lr, -4 311 frame-setup CFI_INSTRUCTION offset $r11, -8 312 frame-setup CFI_INSTRUCTION offset $r10, -12 313 frame-setup CFI_INSTRUCTION offset $r9, -16 314 frame-setup CFI_INSTRUCTION offset $r8, -20 315 frame-setup CFI_INSTRUCTION offset $r7, -24 316 frame-setup CFI_INSTRUCTION offset $r6, -28 317 frame-setup CFI_INSTRUCTION offset $r5, -32 318 frame-setup CFI_INSTRUCTION offset $r4, -36 319 $sp = frame-setup tSUBspi $sp, 10, 14 /* CC::al */, $noreg 320 frame-setup CFI_INSTRUCTION def_cfa_offset 76 321 $r6, $r5 = t2LDRDi8 $r0, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i7), (load (s32) from %ir.i10) 322 $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg 323 $r3, $r7 = t2LDRDi8 killed $r0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i), (load (s32) from %ir.i5) 324 renamable $r0 = t2RSBri killed renamable $r6, 31, 14 /* CC::al */, $noreg, $noreg 325 t2STMIA $sp, 14 /* CC::al */, $noreg, killed $r0, $r2, $r8 :: (store (s32) into %stack.9), (store (s32) into %stack.8), (store (s32) into %stack.7) 326 $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg 327 renamable $r2 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.9) 328 329 bb.1.bb12 (align 4): 330 successors: %bb.2(0x40000000), %bb.5(0x40000000) 331 liveins: $r1, $r3, $r5, $r7, $r8, $r12, $r2 332 333 $r9, $r4 = t2LDRDi8 $r3, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i14), (load (s32) from %ir.i20) 334 $r6, $r0 = t2LDRDi8 $r3, 8, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i22), (load (s32) from %ir.i24) 335 $lr = t2WhileLoopStartLR renamable $r8, %bb.5, implicit-def dead $cpsr 336 tB %bb.2, 14 /* CC::al */, $noreg 337 338 bb.2.bb27: 339 successors: %bb.3(0x80000000) 340 liveins: $r0, $r1, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12, $r2 341 342 t2STRDi8 killed $r3, killed $r5, $sp, 12, 14 /* CC::al */, $noreg :: (store (s32) into %stack.6), (store (s32) into %stack.5) 343 renamable $r3 = tLDRi renamable $r7, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i13) 344 tSTRspi killed renamable $r3, $sp, 9, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) 345 renamable $r3 = tLDRi renamable $r7, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i34) 346 tSTRspi killed renamable $r3, $sp, 8, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1) 347 renamable $r3 = tLDRi renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i32) 348 tSTRspi killed renamable $r3, $sp, 7, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2) 349 renamable $r3 = tLDRi renamable $r7, 3, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i30) 350 t2STRDi8 $r7, killed $r3, $sp, 20, 14 /* CC::al */, $noreg :: (store (s32) into %stack.4), (store (s32) into %stack.3) 351 renamable $r10 = t2LDRi12 killed renamable $r7, 16, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i28) 352 353 bb.3.bb37 (align 4): 354 successors: %bb.3(0x7c000000), %bb.4(0x04000000) 355 liveins: $r0, $r1, $r2, $r4, $r6, $r8, $r9, $r10, $r12 356 357 $r7 = tMOVr killed $r6, 14 /* CC::al */, $noreg 358 renamable $r6 = tLDRspi $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1) 359 renamable $r3 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2) 360 renamable $r6, renamable $r11 = t2SMULL $r9, killed renamable $r6, 14 /* CC::al */, $noreg 361 renamable $r6, renamable $r11 = t2SMLAL killed renamable $r4, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 362 renamable $r3 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load (s32) from %stack.3) 363 $r5 = tMOVr killed $r9, 14 /* CC::al */, $noreg 364 renamable $r6, renamable $r11 = t2SMLAL renamable $r7, killed renamable $r3, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 365 renamable $r9, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.i38) 366 renamable $r6, renamable $r11 = t2SMLAL killed renamable $r0, renamable $r10, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 367 renamable $r0 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 368 $lr = tMOVr $r8, 14 /* CC::al */, $noreg 369 renamable $r6, renamable $r11 = t2SMLAL renamable $r9, killed renamable $r0, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg 370 early-clobber renamable $r6, dead early-clobber renamable $r11 = MVE_ASRLr killed renamable $r6, killed renamable $r11, renamable $r2, 14 /* CC::al */, $noreg 371 early-clobber renamable $r12 = t2STR_POST renamable $r6, killed renamable $r12, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i39) 372 renamable $lr = t2LoopDec killed renamable $lr, 1 373 renamable $r8 = t2SUBri killed renamable $r8, 1, 14 /* CC::al */, $noreg, $noreg 374 $r0 = tMOVr $r7, 14 /* CC::al */, $noreg 375 $r4 = tMOVr $r5, 14 /* CC::al */, $noreg 376 t2LoopEnd killed renamable $lr, %bb.3, implicit-def dead $cpsr 377 tB %bb.4, 14 /* CC::al */, $noreg 378 379 bb.4.bb72: 380 successors: %bb.5(0x80000000) 381 liveins: $r5, $r6, $r7, $r9, $r2 382 383 $r0 = tMOVr killed $r7, 14 /* CC::al */, $noreg 384 $r7 = tADDrSPi $sp, 3, 14 /* CC::al */, $noreg 385 $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg 386 $r12, $r8 = t2LDRDi8 $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %stack.8), (load (s32) from %stack.7) 387 tLDMIA killed $r7, 14 /* CC::al */, $noreg, def $r3, def $r5, def $r7 :: (load (s32) from %stack.6), (load (s32) from %stack.5), (load (s32) from %stack.4) 388 389 bb.5.bb74: 390 successors: %bb.6(0x04000000), %bb.1(0x7c000000) 391 liveins: $r0, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12, $r2 392 393 renamable $r7, dead $cpsr = nuw tADDi8 killed renamable $r7, 20, 14 /* CC::al */, $noreg 394 t2STRDi8 killed $r9, killed $r4, $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i14), (store (s32) into %ir.i81) 395 t2STRDi8 killed $r6, killed $r0, $r3, 8, 14 /* CC::al */, $noreg :: (store (s32) into %ir.i84), (store (s32) into %ir.i88) 396 renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg 397 renamable $r5, $cpsr = tSUBi8 killed renamable $r5, 1, 14 /* CC::al */, $noreg 398 $r1 = tMOVr $r12, 14 /* CC::al */, $noreg 399 tBcc %bb.1, 1 /* CC::ne */, killed $cpsr 400 401 bb.6.bb91: 402 $sp = frame-destroy tADDspi $sp, 10, 14 /* CC::al */, $noreg 403 $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc 404 405... 406