xref: /llvm-project/llvm/test/CodeGen/Thumb/pr35836_2.ll (revision e6bf3fa05b3706197143414a56be05ce014ebe01)
1; RUN: llc < %s | FileCheck %s
2
3target datalayout = "e-m:e-p:64:64-i128:64-v128:64:128-a:0:64-n64-S64"
4target triple = "thumbv6---gnueabi"
5
6; Function Attrs: norecurse nounwind readonly
7define i128 @a(ptr nocapture readonly %z) local_unnamed_addr #0 {
8entry:
9  %0 = load i64, ptr %z, align 4
10  %conv.i = zext i64 %0 to i128
11  %arrayidx1 = getelementptr inbounds i64, ptr %z, i64 2
12  %1 = load i64, ptr %arrayidx1, align 4
13  %conv.i38 = zext i64 %1 to i128
14  %shl.i39 = shl nuw i128 %conv.i38, 64
15  %or = or i128 %shl.i39, %conv.i
16  %arrayidx3 = getelementptr inbounds i64, ptr %z, i64 1
17  %2 = load i64, ptr %arrayidx3, align 4
18  %conv.i37 = zext i64 %2 to i128
19  %arrayidx5 = getelementptr inbounds i64, ptr %z, i64 3
20  %3 = load i64, ptr %arrayidx5, align 4
21  %conv.i35 = zext i64 %3 to i128
22  %shl.i36 = shl nuw i128 %conv.i35, 64
23  %or7 = or i128 %shl.i36, %conv.i37
24  %arrayidx10 = getelementptr inbounds i64, ptr %z, i64 4
25  %4 = load i64, ptr %arrayidx10, align 4
26  %conv.i64 = zext i64 %4 to i128
27  %shl.i33 = shl nuw i128 %conv.i64, 64
28  %or12 = or i128 %shl.i33, %conv.i
29  %arrayidx15 = getelementptr inbounds i64, ptr %z, i64 5
30  %5 = load i64, ptr %arrayidx15, align 4
31  %conv.i30 = zext i64 %5 to i128
32  %shl.i = shl nuw i128 %conv.i30, 64
33  %or17 = or i128 %shl.i, %conv.i37
34  %add = add i128 %or7, %or
35  %add18 = add i128 %or17, %or12
36  %mul = mul i128 %add18, %add
37  ret i128 %mul
38}
39; CHECK: adds r5, r1, r6
40; CHECK: mov r5, r4
41; CHECK: adcs r5, r7
42; CHECK: ldr r5, [sp, #12]                   @ 4-byte Reload
43; CHECK: adcs r2, r5
44; CHECK: ldr r5, [sp, #16]                   @ 4-byte Reload
45; CHECK: adcs r3, r5
46; CHECK: adds r6, r1, r6
47; CHECK: adcs r4, r7
48; CHECK: ldr r1, [r0, #20]
49; CHECK: str r1, [sp, #16]                   @ 4-byte Spill
50; CHECK: ldr r5, [r0, #28]
51; CHECK: ldr r1, [r0, #16]
52; CHECK: ldr r7, [r0, #24]
53; CHECK: adcs r7, r1
54; CHECK: ldr r0, [sp, #16]                   @ 4-byte Reload
55; CHECK: adcs r5, r0
56