xref: /llvm-project/llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll (revision 440c4b705ad1d494a183b53cd65f21a481726157)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumb-eabi %s -verify-machineinstrs -o - | FileCheck %s --check-prefix=THUMB
3; RUN: llc -mtriple=thumbv6-eabi %s -verify-machineinstrs -o - | FileCheck %s --check-prefix=THUMBV6
4
5; The scheduler used to ignore OptionalDefs, and could unwittingly insert
6; a flag-setting instruction in between an ADDS and the corresponding ADC.
7
8; FIXME: The ABS lowering changed to XOR followed by SUB so this may no longer
9; be testing what it used to.
10
11define i1 @test(i64 %arg) {
12; THUMB-LABEL: test:
13; THUMB:       @ %bb.0: @ %entry
14; THUMB-NEXT:    .save {r4, lr}
15; THUMB-NEXT:    push {r4, lr}
16; THUMB-NEXT:    asrs r2, r1, #31
17; THUMB-NEXT:    movs r3, r1
18; THUMB-NEXT:    eors r3, r2
19; THUMB-NEXT:    movs r4, r0
20; THUMB-NEXT:    eors r4, r2
21; THUMB-NEXT:    subs r4, r4, r2
22; THUMB-NEXT:    sbcs r3, r2
23; THUMB-NEXT:    eors r3, r1
24; THUMB-NEXT:    eors r0, r4
25; THUMB-NEXT:    orrs r0, r3
26; THUMB-NEXT:    rsbs r1, r0, #0
27; THUMB-NEXT:    adcs r0, r1
28; THUMB-NEXT:    pop {r4}
29; THUMB-NEXT:    pop {r1}
30; THUMB-NEXT:    bx r1
31;
32; THUMBV6-LABEL: test:
33; THUMBV6:       @ %bb.0: @ %entry
34; THUMBV6-NEXT:    .save {r4, lr}
35; THUMBV6-NEXT:    push {r4, lr}
36; THUMBV6-NEXT:    asrs r2, r1, #31
37; THUMBV6-NEXT:    mov r3, r1
38; THUMBV6-NEXT:    eors r3, r2
39; THUMBV6-NEXT:    mov r4, r0
40; THUMBV6-NEXT:    eors r4, r2
41; THUMBV6-NEXT:    subs r4, r4, r2
42; THUMBV6-NEXT:    sbcs r3, r2
43; THUMBV6-NEXT:    eors r3, r1
44; THUMBV6-NEXT:    eors r0, r4
45; THUMBV6-NEXT:    orrs r0, r3
46; THUMBV6-NEXT:    rsbs r1, r0, #0
47; THUMBV6-NEXT:    adcs r0, r1
48; THUMBV6-NEXT:    pop {r4, pc}
49entry:
50  %ispos = icmp sgt i64 %arg, -1
51  %neg = sub i64 0, %arg
52  %sel = select i1 %ispos, i64 %arg, i64 %neg
53  %cmp2 = icmp eq i64 %sel, %arg
54  ret i1 %cmp2
55}
56