xref: /llvm-project/llvm/test/CodeGen/Thumb/iabs-vector.ll (revision e6bf3fa05b3706197143414a56be05ce014ebe01)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=thumbv7--- | FileCheck %s
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4define void @PR41160(ptr %p) nounwind {
5; CHECK-LABEL: PR41160:
6; CHECK:       @ %bb.0:
7; CHECK-NEXT:    vld1.8 {d16, d17}, [r0]
8; CHECK-NEXT:    vabs.s32 q8, q8
9; CHECK-NEXT:    vst1.8 {d16, d17}, [r0]!
10; CHECK-NEXT:    vld1.8 {d16, d17}, [r0]
11; CHECK-NEXT:    vabs.s32 q8, q8
12; CHECK-NEXT:    vst1.8 {d16, d17}, [r0]
13; CHECK-NEXT:    bx lr
14  %tmp1 = load <8 x i32>, ptr %p, align 1
15  %tmp2 = icmp slt <8 x i32> %tmp1, zeroinitializer
16  %tmp3 = sub nsw <8 x i32> zeroinitializer, %tmp1
17  %tmp4 = select <8 x i1> %tmp2, <8 x i32> %tmp3, <8 x i32> %tmp1
18  store <8 x i32> %tmp4, ptr %p, align 1
19  ret void
20}
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