xref: /llvm-project/llvm/test/CodeGen/Thumb/bic_imm.ll (revision e6bf3fa05b3706197143414a56be05ce014ebe01)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=cortex-m0 -verify-machineinstrs | FileCheck --check-prefix CHECK-T1 %s
3; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=cortex-m3 -verify-machineinstrs | FileCheck --check-prefix CHECK-T2 %s
4
5define i32 @i(i32 %a) {
6; CHECK-T1-LABEL: i:
7; CHECK-T1:       @ %bb.0: @ %entry
8; CHECK-T1-NEXT:    movs r1, #255
9; CHECK-T1-NEXT:    adds r1, #20
10; CHECK-T1-NEXT:    bics r0, r1
11; CHECK-T1-NEXT:    bx lr
12;
13; CHECK-T2-LABEL: i:
14; CHECK-T2:       @ %bb.0: @ %entry
15; CHECK-T2-NEXT:    movw r1, #275
16; CHECK-T2-NEXT:    bics r0, r1
17; CHECK-T2-NEXT:    bx lr
18entry:
19  %and = and i32 %a, -276
20  ret i32 %and
21}
22
23define i32 @j(i32 %a) {
24; CHECK-T1-LABEL: j:
25; CHECK-T1:       @ %bb.0: @ %entry
26; CHECK-T1-NEXT:    movs r1, #128
27; CHECK-T1-NEXT:    bics r0, r1
28; CHECK-T1-NEXT:    bx lr
29;
30; CHECK-T2-LABEL: j:
31; CHECK-T2:       @ %bb.0: @ %entry
32; CHECK-T2-NEXT:    bic r0, r0, #128
33; CHECK-T2-NEXT:    bx lr
34entry:
35  %and = and i32 %a, -129
36  ret i32 %and
37}
38
39define void @truncated(i16 %a, ptr %p) {
40; CHECK-T1-LABEL: truncated:
41; CHECK-T1:       @ %bb.0:
42; CHECK-T1-NEXT:    movs r2, #128
43; CHECK-T1-NEXT:    bics r0, r2
44; CHECK-T1-NEXT:    strh r0, [r1]
45; CHECK-T1-NEXT:    bx lr
46;
47; CHECK-T2-LABEL: truncated:
48; CHECK-T2:       @ %bb.0:
49; CHECK-T2-NEXT:    bic r0, r0, #128
50; CHECK-T2-NEXT:    strh r0, [r1]
51; CHECK-T2-NEXT:    bx lr
52  %and = and i16 %a, -129
53  store i16 %and, ptr %p
54  ret void
55}
56
57define void @truncated_neg2(i16 %a, ptr %p) {
58; CHECK-T1-LABEL: truncated_neg2:
59; CHECK-T1:       @ %bb.0:
60; CHECK-T1-NEXT:    movs r2, #1
61; CHECK-T1-NEXT:    bics r0, r2
62; CHECK-T1-NEXT:    strh r0, [r1]
63; CHECK-T1-NEXT:    bx lr
64;
65; CHECK-T2-LABEL: truncated_neg2:
66; CHECK-T2:       @ %bb.0:
67; CHECK-T2-NEXT:    bic r0, r0, #1
68; CHECK-T2-NEXT:    strh r0, [r1]
69; CHECK-T2-NEXT:    bx lr
70  %and = and i16 %a, -2
71  store i16 %and, ptr %p
72  ret void
73}
74
75define void @truncated_neg256(i16 %a, ptr %p) {
76; CHECK-T1-LABEL: truncated_neg256:
77; CHECK-T1:       @ %bb.0:
78; CHECK-T1-NEXT:    movs r2, #255
79; CHECK-T1-NEXT:    bics r0, r2
80; CHECK-T1-NEXT:    strh r0, [r1]
81; CHECK-T1-NEXT:    bx lr
82;
83; CHECK-T2-LABEL: truncated_neg256:
84; CHECK-T2:       @ %bb.0:
85; CHECK-T2-NEXT:    bic r0, r0, #255
86; CHECK-T2-NEXT:    strh r0, [r1]
87; CHECK-T2-NEXT:    bx lr
88  %and = and i16 %a, -256
89  store i16 %and, ptr %p
90  ret void
91}
92
93; FIXME: Thumb2 supports "bic r0, r0, #510"
94define void @truncated_neg511(i16 %a, ptr %p) {
95; CHECK-T1-LABEL: truncated_neg511:
96; CHECK-T1:       @ %bb.0:
97; CHECK-T1-NEXT:    ldr r2, .LCPI5_0
98; CHECK-T1-NEXT:    ands r2, r0
99; CHECK-T1-NEXT:    strh r2, [r1]
100; CHECK-T1-NEXT:    bx lr
101; CHECK-T1-NEXT:    .p2align 2
102; CHECK-T1-NEXT:  @ %bb.1:
103; CHECK-T1-NEXT:  .LCPI5_0:
104; CHECK-T1-NEXT:    .long 65025 @ 0xfe01
105;
106; CHECK-T2-LABEL: truncated_neg511:
107; CHECK-T2:       @ %bb.0:
108; CHECK-T2-NEXT:    movw r2, #65025
109; CHECK-T2-NEXT:    ands r0, r2
110; CHECK-T2-NEXT:    strh r0, [r1]
111; CHECK-T2-NEXT:    bx lr
112  %and = and i16 %a, -511
113  store i16 %and, ptr %p
114  ret void
115}
116