xref: /llvm-project/llvm/test/CodeGen/SystemZ/vec-move-03.ll (revision a1710eb3cd5823c5d14899112ca3086acbdbe9cb) 
1; Test vector stores.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
4
5; Test v16i8 stores.
6define void @f1(<16 x i8> %val, ptr %ptr) {
7; CHECK-LABEL: f1:
8; CHECK: vst %v24, 0(%r2), 3
9; CHECK: br %r14
10  store <16 x i8> %val, ptr %ptr
11  ret void
12}
13
14; Test v8i16 stores.
15define void @f2(<8 x i16> %val, ptr %ptr) {
16; CHECK-LABEL: f2:
17; CHECK: vst %v24, 0(%r2), 3
18; CHECK: br %r14
19  store <8 x i16> %val, ptr %ptr
20  ret void
21}
22
23; Test v4i32 stores.
24define void @f3(<4 x i32> %val, ptr %ptr) {
25; CHECK-LABEL: f3:
26; CHECK: vst %v24, 0(%r2), 3
27; CHECK: br %r14
28  store <4 x i32> %val, ptr %ptr
29  ret void
30}
31
32; Test v2i64 stores.
33define void @f4(<2 x i64> %val, ptr %ptr) {
34; CHECK-LABEL: f4:
35; CHECK: vst %v24, 0(%r2), 3
36; CHECK: br %r14
37  store <2 x i64> %val, ptr %ptr
38  ret void
39}
40
41; Test v4f32 stores.
42define void @f5(<4 x float> %val, ptr %ptr) {
43; CHECK-LABEL: f5:
44; CHECK: vst %v24, 0(%r2), 3
45; CHECK: br %r14
46  store <4 x float> %val, ptr %ptr
47  ret void
48}
49
50; Test v2f64 stores.
51define void @f6(<2 x double> %val, ptr %ptr) {
52; CHECK-LABEL: f6:
53; CHECK: vst %v24, 0(%r2), 3
54; CHECK: br %r14
55  store <2 x double> %val, ptr %ptr
56  ret void
57}
58
59; Test the highest aligned in-range offset.
60define void @f7(<16 x i8> %val, ptr %base) {
61; CHECK-LABEL: f7:
62; CHECK: vst %v24, 4080(%r2), 3
63; CHECK: br %r14
64  %ptr = getelementptr <16 x i8>, ptr %base, i64 255
65  store <16 x i8> %val, ptr %ptr
66  ret void
67}
68
69; Test the highest unaligned in-range offset.
70define void @f8(<16 x i8> %val, ptr %base) {
71; CHECK-LABEL: f8:
72; CHECK: vst %v24, 4095(%r2)
73; CHECK: br %r14
74  %addr = getelementptr i8, ptr %base, i64 4095
75  store <16 x i8> %val, ptr %addr, align 1
76  ret void
77}
78
79; Test the next offset up, which requires separate address logic,
80define void @f9(<16 x i8> %val, ptr %base) {
81; CHECK-LABEL: f9:
82; CHECK: aghi %r2, 4096
83; CHECK: vst %v24, 0(%r2), 3
84; CHECK: br %r14
85  %ptr = getelementptr <16 x i8>, ptr %base, i64 256
86  store <16 x i8> %val, ptr %ptr
87  ret void
88}
89
90; Test negative offsets, which also require separate address logic,
91define void @f10(<16 x i8> %val, ptr %base) {
92; CHECK-LABEL: f10:
93; CHECK: aghi %r2, -16
94; CHECK: vst %v24, 0(%r2), 3
95; CHECK: br %r14
96  %ptr = getelementptr <16 x i8>, ptr %base, i64 -1
97  store <16 x i8> %val, ptr %ptr
98  ret void
99}
100
101; Check that indexes are allowed.
102define void @f11(<16 x i8> %val, ptr %base, i64 %index) {
103; CHECK-LABEL: f11:
104; CHECK: vst %v24, 0(%r3,%r2)
105; CHECK: br %r14
106  %addr = getelementptr i8, ptr %base, i64 %index
107  store <16 x i8> %val, ptr %addr, align 1
108  ret void
109}
110
111; Test v2i8 stores.
112define void @f12(<2 x i8> %val, ptr %ptr) {
113; CHECK-LABEL: f12:
114; CHECK: vsteh %v24, 0(%r2), 0
115; CHECK: br %r14
116  store <2 x i8> %val, ptr %ptr
117  ret void
118}
119
120; Test v4i8 stores.
121define void @f13(<4 x i8> %val, ptr %ptr) {
122; CHECK-LABEL: f13:
123; CHECK: vstef %v24, 0(%r2)
124; CHECK: br %r14
125  store <4 x i8> %val, ptr %ptr
126  ret void
127}
128
129; Test v8i8 stores.
130define void @f14(<8 x i8> %val, ptr %ptr) {
131; CHECK-LABEL: f14:
132; CHECK: vsteg %v24, 0(%r2)
133; CHECK: br %r14
134  store <8 x i8> %val, ptr %ptr
135  ret void
136}
137
138; Test v2i16 stores.
139define void @f15(<2 x i16> %val, ptr %ptr) {
140; CHECK-LABEL: f15:
141; CHECK: vstef %v24, 0(%r2), 0
142; CHECK: br %r14
143  store <2 x i16> %val, ptr %ptr
144  ret void
145}
146
147; Test v4i16 stores.
148define void @f16(<4 x i16> %val, ptr %ptr) {
149; CHECK-LABEL: f16:
150; CHECK: vsteg %v24, 0(%r2)
151; CHECK: br %r14
152  store <4 x i16> %val, ptr %ptr
153  ret void
154}
155
156; Test v2i32 stores.
157define void @f17(<2 x i32> %val, ptr %ptr) {
158; CHECK-LABEL: f17:
159; CHECK: vsteg %v24, 0(%r2), 0
160; CHECK: br %r14
161  store <2 x i32> %val, ptr %ptr
162  ret void
163}
164
165; Test v2f32 stores.
166define void @f18(<2 x float> %val, ptr %ptr) {
167; CHECK-LABEL: f18:
168; CHECK: vsteg %v24, 0(%r2), 0
169; CHECK: br %r14
170  store <2 x float> %val, ptr %ptr
171  ret void
172}
173
174; Test quadword-aligned stores.
175define void @f19(<16 x i8> %val, ptr %ptr) {
176; CHECK-LABEL: f19:
177; CHECK: vst %v24, 0(%r2), 4
178; CHECK: br %r14
179  store <16 x i8> %val, ptr %ptr, align 16
180  ret void
181}
182
183; Test that the alignment hint for VST is emitted also when CFG optimizer
184; replaces two VSTs with just one that then carries two memoperands.
185define void @f20() {
186; CHECK-LABEL: f20:
187; CHECK: vst %v0, 0(%r1), 3
188; CHECK-NOT: vst
189entry:
190  switch i32 undef, label %exit [
191    i32 1, label %bb1
192    i32 2, label %bb2
193  ]
194
195bb1:
196  %C1 = call ptr @foo()
197  %I1 = insertelement <2 x ptr> poison, ptr %C1, i64 0
198  %S1 = shufflevector <2 x ptr> %I1, <2 x ptr> poison, <2 x i32> zeroinitializer
199  store <2 x ptr> %S1, ptr undef, align 8
200  br label %exit
201
202bb2:
203  %C2 = call ptr @foo()
204  %I2 = insertelement <2 x ptr> poison, ptr %C2, i64 0
205  %S2 = shufflevector <2 x ptr> %I2, <2 x ptr> poison, <2 x i32> zeroinitializer
206  store <2 x ptr> %S2, ptr undef, align 8
207  br label %exit
208
209exit:
210  ret void
211}
212
213declare ptr @foo()
214