1; Test vector loads. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 4 5; Test v16i8 loads. 6define <16 x i8> @f1(ptr %ptr) { 7; CHECK-LABEL: f1: 8; CHECK: vl %v24, 0(%r2), 3 9; CHECK: br %r14 10 %ret = load <16 x i8>, ptr %ptr 11 ret <16 x i8> %ret 12} 13 14; Test v8i16 loads. 15define <8 x i16> @f2(ptr %ptr) { 16; CHECK-LABEL: f2: 17; CHECK: vl %v24, 0(%r2), 3 18; CHECK: br %r14 19 %ret = load <8 x i16>, ptr %ptr 20 ret <8 x i16> %ret 21} 22 23; Test v4i32 loads. 24define <4 x i32> @f3(ptr %ptr) { 25; CHECK-LABEL: f3: 26; CHECK: vl %v24, 0(%r2), 3 27; CHECK: br %r14 28 %ret = load <4 x i32>, ptr %ptr 29 ret <4 x i32> %ret 30} 31 32; Test v2i64 loads. 33define <2 x i64> @f4(ptr %ptr) { 34; CHECK-LABEL: f4: 35; CHECK: vl %v24, 0(%r2), 3 36; CHECK: br %r14 37 %ret = load <2 x i64>, ptr %ptr 38 ret <2 x i64> %ret 39} 40 41; Test v4f32 loads. 42define <4 x float> @f5(ptr %ptr) { 43; CHECK-LABEL: f5: 44; CHECK: vl %v24, 0(%r2), 3 45; CHECK: br %r14 46 %ret = load <4 x float>, ptr %ptr 47 ret <4 x float> %ret 48} 49 50; Test v2f64 loads. 51define <2 x double> @f6(ptr %ptr) { 52; CHECK-LABEL: f6: 53; CHECK: vl %v24, 0(%r2), 3 54; CHECK: br %r14 55 %ret = load <2 x double>, ptr %ptr 56 ret <2 x double> %ret 57} 58 59; Test the highest aligned in-range offset. 60define <16 x i8> @f7(ptr %base) { 61; CHECK-LABEL: f7: 62; CHECK: vl %v24, 4080(%r2), 3 63; CHECK: br %r14 64 %ptr = getelementptr <16 x i8>, ptr %base, i64 255 65 %ret = load <16 x i8>, ptr %ptr 66 ret <16 x i8> %ret 67} 68 69; Test the highest unaligned in-range offset. 70define <16 x i8> @f8(ptr %base) { 71; CHECK-LABEL: f8: 72; CHECK: vl %v24, 4095(%r2) 73; CHECK: br %r14 74 %addr = getelementptr i8, ptr %base, i64 4095 75 %ret = load <16 x i8>, ptr %addr, align 1 76 ret <16 x i8> %ret 77} 78 79; Test the next offset up, which requires separate address logic, 80define <16 x i8> @f9(ptr %base) { 81; CHECK-LABEL: f9: 82; CHECK: aghi %r2, 4096 83; CHECK: vl %v24, 0(%r2), 3 84; CHECK: br %r14 85 %ptr = getelementptr <16 x i8>, ptr %base, i64 256 86 %ret = load <16 x i8>, ptr %ptr 87 ret <16 x i8> %ret 88} 89 90; Test negative offsets, which also require separate address logic, 91define <16 x i8> @f10(ptr %base) { 92; CHECK-LABEL: f10: 93; CHECK: aghi %r2, -16 94; CHECK: vl %v24, 0(%r2), 3 95; CHECK: br %r14 96 %ptr = getelementptr <16 x i8>, ptr %base, i64 -1 97 %ret = load <16 x i8>, ptr %ptr 98 ret <16 x i8> %ret 99} 100 101; Check that indexes are allowed. 102define <16 x i8> @f11(ptr %base, i64 %index) { 103; CHECK-LABEL: f11: 104; CHECK: vl %v24, 0(%r3,%r2) 105; CHECK: br %r14 106 %addr = getelementptr i8, ptr %base, i64 %index 107 %ret = load <16 x i8>, ptr %addr, align 1 108 ret <16 x i8> %ret 109} 110 111; Test v2i8 loads. 112define <2 x i8> @f12(ptr %ptr) { 113; CHECK-LABEL: f12: 114; CHECK: vlreph %v24, 0(%r2) 115; CHECK: br %r14 116 %ret = load <2 x i8>, ptr %ptr 117 ret <2 x i8> %ret 118} 119 120; Test v4i8 loads. 121define <4 x i8> @f13(ptr %ptr) { 122; CHECK-LABEL: f13: 123; CHECK: vlrepf %v24, 0(%r2) 124; CHECK: br %r14 125 %ret = load <4 x i8>, ptr %ptr 126 ret <4 x i8> %ret 127} 128 129; Test v8i8 loads. 130define <8 x i8> @f14(ptr %ptr) { 131; CHECK-LABEL: f14: 132; CHECK: vlrepg %v24, 0(%r2) 133; CHECK: br %r14 134 %ret = load <8 x i8>, ptr %ptr 135 ret <8 x i8> %ret 136} 137 138; Test v2i16 loads. 139define <2 x i16> @f15(ptr %ptr) { 140; CHECK-LABEL: f15: 141; CHECK: vlrepf %v24, 0(%r2) 142; CHECK: br %r14 143 %ret = load <2 x i16>, ptr %ptr 144 ret <2 x i16> %ret 145} 146 147; Test v4i16 loads. 148define <4 x i16> @f16(ptr %ptr) { 149; CHECK-LABEL: f16: 150; CHECK: vlrepg %v24, 0(%r2) 151; CHECK: br %r14 152 %ret = load <4 x i16>, ptr %ptr 153 ret <4 x i16> %ret 154} 155 156; Test v2i32 loads. 157define <2 x i32> @f17(ptr %ptr) { 158; CHECK-LABEL: f17: 159; CHECK: vlrepg %v24, 0(%r2) 160; CHECK: br %r14 161 %ret = load <2 x i32>, ptr %ptr 162 ret <2 x i32> %ret 163} 164 165; Test v2f32 loads. 166define <2 x float> @f18(ptr %ptr) { 167; CHECK-LABEL: f18: 168; CHECK: vlrepg %v24, 0(%r2) 169; CHECK: br %r14 170 %ret = load <2 x float>, ptr %ptr 171 ret <2 x float> %ret 172} 173 174; Test quadword-aligned loads. 175define <16 x i8> @f19(ptr %ptr) { 176; CHECK-LABEL: f19: 177; CHECK: vl %v24, 0(%r2), 4 178; CHECK: br %r14 179 %ret = load <16 x i8>, ptr %ptr, align 16 180 ret <16 x i8> %ret 181} 182 183