1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; Test vector intrinsics added with z14. 3; 4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s 5 6declare <2 x i64> @llvm.s390.vbperm(<16 x i8>, <16 x i8>) 7declare i128 @llvm.s390.vmslg(<2 x i64>, <2 x i64>, i128, i32) 8declare <16 x i8> @llvm.s390.vlrl(i32, ptr) 9declare void @llvm.s390.vstrl(<16 x i8>, i32, ptr) 10 11declare {<4 x i32>, i32} @llvm.s390.vfcesbs(<4 x float>, <4 x float>) 12declare {<4 x i32>, i32} @llvm.s390.vfchsbs(<4 x float>, <4 x float>) 13declare {<4 x i32>, i32} @llvm.s390.vfchesbs(<4 x float>, <4 x float>) 14declare {<4 x i32>, i32} @llvm.s390.vftcisb(<4 x float>, i32) 15declare <4 x float> @llvm.s390.vfisb(<4 x float>, i32, i32) 16 17declare <2 x double> @llvm.s390.vfmaxdb(<2 x double>, <2 x double>, i32) 18declare <2 x double> @llvm.s390.vfmindb(<2 x double>, <2 x double>, i32) 19declare <4 x float> @llvm.s390.vfmaxsb(<4 x float>, <4 x float>, i32) 20declare <4 x float> @llvm.s390.vfminsb(<4 x float>, <4 x float>, i32) 21 22; VBPERM. 23define <2 x i64> @test_vbperm(<16 x i8> %a, <16 x i8> %b) { 24; CHECK-LABEL: test_vbperm: 25; CHECK: # %bb.0: 26; CHECK-NEXT: vbperm %v24, %v24, %v26 27; CHECK-NEXT: br %r14 28 %res = call <2 x i64> @llvm.s390.vbperm(<16 x i8> %a, <16 x i8> %b) 29 ret <2 x i64> %res 30} 31 32; VMSLG with no shifts. 33define i128 @test_vmslg1(<2 x i64> %a, <2 x i64> %b, i128 %c) { 34; CHECK-LABEL: test_vmslg1: 35; CHECK: # %bb.0: 36; CHECK-NEXT: vl %v0, 0(%r3), 3 37; CHECK-NEXT: vmslg %v0, %v24, %v26, %v0, 0 38; CHECK-NEXT: vst %v0, 0(%r2), 3 39; CHECK-NEXT: br %r14 40 %res = call i128 @llvm.s390.vmslg(<2 x i64> %a, <2 x i64> %b, i128 %c, i32 0) 41 ret i128 %res 42} 43 44; VMSLG with both shifts. 45define i128 @test_vmslg2(<2 x i64> %a, <2 x i64> %b, i128 %c) { 46; CHECK-LABEL: test_vmslg2: 47; CHECK: # %bb.0: 48; CHECK-NEXT: vl %v0, 0(%r3), 3 49; CHECK-NEXT: vmslg %v0, %v24, %v26, %v0, 12 50; CHECK-NEXT: vst %v0, 0(%r2), 3 51; CHECK-NEXT: br %r14 52 %res = call i128 @llvm.s390.vmslg(<2 x i64> %a, <2 x i64> %b, i128 %c, i32 12) 53 ret i128 %res 54} 55 56; VLRLR with the lowest in-range displacement. 57define <16 x i8> @test_vlrlr1(ptr %ptr, i32 %length) { 58; CHECK-LABEL: test_vlrlr1: 59; CHECK: # %bb.0: 60; CHECK-NEXT: vlrlr %v24, %r3, 0(%r2) 61; CHECK-NEXT: br %r14 62 %res = call <16 x i8> @llvm.s390.vlrl(i32 %length, ptr %ptr) 63 ret <16 x i8> %res 64} 65 66; VLRLR with the highest in-range displacement. 67define <16 x i8> @test_vlrlr2(ptr %base, i32 %length) { 68; CHECK-LABEL: test_vlrlr2: 69; CHECK: # %bb.0: 70; CHECK-NEXT: vlrlr %v24, %r3, 4095(%r2) 71; CHECK-NEXT: br %r14 72 %ptr = getelementptr i8, ptr %base, i64 4095 73 %res = call <16 x i8> @llvm.s390.vlrl(i32 %length, ptr %ptr) 74 ret <16 x i8> %res 75} 76 77; VLRLR with an out-of-range displacement. 78define <16 x i8> @test_vlrlr3(ptr %base, i32 %length) { 79; CHECK-LABEL: test_vlrlr3: 80; CHECK: # %bb.0: 81; CHECK-NEXT: aghi %r2, 4096 82; CHECK-NEXT: vlrlr %v24, %r3, 0(%r2) 83; CHECK-NEXT: br %r14 84 %ptr = getelementptr i8, ptr %base, i64 4096 85 %res = call <16 x i8> @llvm.s390.vlrl(i32 %length, ptr %ptr) 86 ret <16 x i8> %res 87} 88 89; Check that VLRLR doesn't allow an index. 90define <16 x i8> @test_vlrlr4(ptr %base, i64 %index, i32 %length) { 91; CHECK-LABEL: test_vlrlr4: 92; CHECK: # %bb.0: 93; CHECK-NEXT: agr %r2, %r3 94; CHECK-NEXT: vlrlr %v24, %r4, 0(%r2) 95; CHECK-NEXT: br %r14 96 %ptr = getelementptr i8, ptr %base, i64 %index 97 %res = call <16 x i8> @llvm.s390.vlrl(i32 %length, ptr %ptr) 98 ret <16 x i8> %res 99} 100 101; VLRL with the lowest in-range displacement. 102define <16 x i8> @test_vlrl1(ptr %ptr) { 103; CHECK-LABEL: test_vlrl1: 104; CHECK: # %bb.0: 105; CHECK-NEXT: vlrl %v24, 0(%r2), 0 106; CHECK-NEXT: br %r14 107 %res = call <16 x i8> @llvm.s390.vlrl(i32 0, ptr %ptr) 108 ret <16 x i8> %res 109} 110 111; VLRL with the highest in-range displacement. 112define <16 x i8> @test_vlrl2(ptr %base) { 113; CHECK-LABEL: test_vlrl2: 114; CHECK: # %bb.0: 115; CHECK-NEXT: vlrl %v24, 4095(%r2), 0 116; CHECK-NEXT: br %r14 117 %ptr = getelementptr i8, ptr %base, i64 4095 118 %res = call <16 x i8> @llvm.s390.vlrl(i32 0, ptr %ptr) 119 ret <16 x i8> %res 120} 121 122; VLRL with an out-of-range displacement. 123define <16 x i8> @test_vlrl3(ptr %base) { 124; CHECK-LABEL: test_vlrl3: 125; CHECK: # %bb.0: 126; CHECK-NEXT: aghi %r2, 4096 127; CHECK-NEXT: vlrl %v24, 0(%r2), 0 128; CHECK-NEXT: br %r14 129 %ptr = getelementptr i8, ptr %base, i64 4096 130 %res = call <16 x i8> @llvm.s390.vlrl(i32 0, ptr %ptr) 131 ret <16 x i8> %res 132} 133 134; Check that VLRL doesn't allow an index. 135define <16 x i8> @test_vlrl4(ptr %base, i64 %index) { 136; CHECK-LABEL: test_vlrl4: 137; CHECK: # %bb.0: 138; CHECK-NEXT: agr %r2, %r3 139; CHECK-NEXT: vlrl %v24, 0(%r2), 0 140; CHECK-NEXT: br %r14 141 %ptr = getelementptr i8, ptr %base, i64 %index 142 %res = call <16 x i8> @llvm.s390.vlrl(i32 0, ptr %ptr) 143 ret <16 x i8> %res 144} 145 146; VLRL with length >= 15 should become VL. 147define <16 x i8> @test_vlrl5(ptr %ptr) { 148; CHECK-LABEL: test_vlrl5: 149; CHECK: # %bb.0: 150; CHECK-NEXT: vl %v24, 0(%r2), 3 151; CHECK-NEXT: br %r14 152 %res = call <16 x i8> @llvm.s390.vlrl(i32 15, ptr %ptr) 153 ret <16 x i8> %res 154} 155 156; VSTRLR with the lowest in-range displacement. 157define void @test_vstrlr1(<16 x i8> %vec, ptr %ptr, i32 %length) { 158; CHECK-LABEL: test_vstrlr1: 159; CHECK: # %bb.0: 160; CHECK-NEXT: vstrlr %v24, %r3, 0(%r2) 161; CHECK-NEXT: br %r14 162 call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, ptr %ptr) 163 ret void 164} 165 166; VSTRLR with the highest in-range displacement. 167define void @test_vstrlr2(<16 x i8> %vec, ptr %base, i32 %length) { 168; CHECK-LABEL: test_vstrlr2: 169; CHECK: # %bb.0: 170; CHECK-NEXT: vstrlr %v24, %r3, 4095(%r2) 171; CHECK-NEXT: br %r14 172 %ptr = getelementptr i8, ptr %base, i64 4095 173 call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, ptr %ptr) 174 ret void 175} 176 177; VSTRLR with an out-of-range displacement. 178define void @test_vstrlr3(<16 x i8> %vec, ptr %base, i32 %length) { 179; CHECK-LABEL: test_vstrlr3: 180; CHECK: # %bb.0: 181; CHECK-NEXT: aghi %r2, 4096 182; CHECK-NEXT: vstrlr %v24, %r3, 0(%r2) 183; CHECK-NEXT: br %r14 184 %ptr = getelementptr i8, ptr %base, i64 4096 185 call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, ptr %ptr) 186 ret void 187} 188 189; Check that VSTRLR doesn't allow an index. 190define void @test_vstrlr4(<16 x i8> %vec, ptr %base, i64 %index, i32 %length) { 191; CHECK-LABEL: test_vstrlr4: 192; CHECK: # %bb.0: 193; CHECK-NEXT: agr %r2, %r3 194; CHECK-NEXT: vstrlr %v24, %r4, 0(%r2) 195; CHECK-NEXT: br %r14 196 %ptr = getelementptr i8, ptr %base, i64 %index 197 call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, ptr %ptr) 198 ret void 199} 200 201; VSTRL with the lowest in-range displacement. 202define void @test_vstrl1(<16 x i8> %vec, ptr %ptr) { 203; CHECK-LABEL: test_vstrl1: 204; CHECK: # %bb.0: 205; CHECK-NEXT: vstrl %v24, 0(%r2), 8 206; CHECK-NEXT: br %r14 207 call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, ptr %ptr) 208 ret void 209} 210 211; VSTRL with the highest in-range displacement. 212define void @test_vstrl2(<16 x i8> %vec, ptr %base) { 213; CHECK-LABEL: test_vstrl2: 214; CHECK: # %bb.0: 215; CHECK-NEXT: vstrl %v24, 4095(%r2), 8 216; CHECK-NEXT: br %r14 217 %ptr = getelementptr i8, ptr %base, i64 4095 218 call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, ptr %ptr) 219 ret void 220} 221 222; VSTRL with an out-of-range displacement. 223define void @test_vstrl3(<16 x i8> %vec, ptr %base) { 224; CHECK-LABEL: test_vstrl3: 225; CHECK: # %bb.0: 226; CHECK-NEXT: aghi %r2, 4096 227; CHECK-NEXT: vstrl %v24, 0(%r2), 8 228; CHECK-NEXT: br %r14 229 %ptr = getelementptr i8, ptr %base, i64 4096 230 call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, ptr %ptr) 231 ret void 232} 233 234; Check that VSTRL doesn't allow an index. 235define void @test_vstrl4(<16 x i8> %vec, ptr %base, i64 %index) { 236; CHECK-LABEL: test_vstrl4: 237; CHECK: # %bb.0: 238; CHECK-NEXT: agr %r2, %r3 239; CHECK-NEXT: vstrl %v24, 0(%r2), 8 240; CHECK-NEXT: br %r14 241 %ptr = getelementptr i8, ptr %base, i64 %index 242 call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, ptr %ptr) 243 ret void 244} 245 246; VSTRL with length >= 15 should become VST. 247define void @test_vstrl5(<16 x i8> %vec, ptr %ptr) { 248; CHECK-LABEL: test_vstrl5: 249; CHECK: # %bb.0: 250; CHECK-NEXT: vst %v24, 0(%r2), 3 251; CHECK-NEXT: br %r14 252 call void @llvm.s390.vstrl(<16 x i8> %vec, i32 15, ptr %ptr) 253 ret void 254} 255 256; VFCESBS with no processing of the result. 257define i32 @test_vfcesbs(<4 x float> %a, <4 x float> %b) { 258; CHECK-LABEL: test_vfcesbs: 259; CHECK: # %bb.0: 260; CHECK-NEXT: vfcesbs %v0, %v24, %v26 261; CHECK-NEXT: ipm %r2 262; CHECK-NEXT: srl %r2, 28 263; CHECK-NEXT: br %r14 264 %call = call {<4 x i32>, i32} @llvm.s390.vfcesbs(<4 x float> %a, 265 <4 x float> %b) 266 %res = extractvalue {<4 x i32>, i32} %call, 1 267 ret i32 %res 268} 269 270; VFCESBS, returning 1 if any elements are equal (CC != 3). 271define i32 @test_vfcesbs_any_bool(<4 x float> %a, <4 x float> %b) { 272; CHECK-LABEL: test_vfcesbs_any_bool: 273; CHECK: # %bb.0: 274; CHECK-NEXT: vfcesbs %v0, %v24, %v26 275; CHECK-NEXT: lhi %r2, 0 276; CHECK-NEXT: lochile %r2, 1 277; CHECK-NEXT: br %r14 278 %call = call {<4 x i32>, i32} @llvm.s390.vfcesbs(<4 x float> %a, 279 <4 x float> %b) 280 %res = extractvalue {<4 x i32>, i32} %call, 1 281 %cmp = icmp ne i32 %res, 3 282 %ext = zext i1 %cmp to i32 283 ret i32 %ext 284} 285 286; VFCESBS, storing to %ptr if any elements are equal. 287define <4 x i32> @test_vfcesbs_any_store(<4 x float> %a, <4 x float> %b, 288; CHECK-LABEL: test_vfcesbs_any_store: 289; CHECK: # %bb.0: 290; CHECK-NEXT: vfcesbs %v24, %v24, %v26 291; CHECK-NEXT: bor %r14 292; CHECK-NEXT: .LBB23_1: # %store 293; CHECK-NEXT: mvhi 0(%r2), 0 294; CHECK-NEXT: br %r14 295 ptr %ptr) { 296 %call = call {<4 x i32>, i32} @llvm.s390.vfcesbs(<4 x float> %a, 297 <4 x float> %b) 298 %res = extractvalue {<4 x i32>, i32} %call, 0 299 %cc = extractvalue {<4 x i32>, i32} %call, 1 300 %cmp = icmp ule i32 %cc, 2 301 br i1 %cmp, label %store, label %exit 302 303store: 304 store i32 0, ptr %ptr 305 br label %exit 306 307exit: 308 ret <4 x i32> %res 309} 310 311; VFCHSBS with no processing of the result. 312define i32 @test_vfchsbs(<4 x float> %a, <4 x float> %b) { 313; CHECK-LABEL: test_vfchsbs: 314; CHECK: # %bb.0: 315; CHECK-NEXT: vfchsbs %v0, %v24, %v26 316; CHECK-NEXT: ipm %r2 317; CHECK-NEXT: srl %r2, 28 318; CHECK-NEXT: br %r14 319 %call = call {<4 x i32>, i32} @llvm.s390.vfchsbs(<4 x float> %a, 320 <4 x float> %b) 321 %res = extractvalue {<4 x i32>, i32} %call, 1 322 ret i32 %res 323} 324 325; VFCHSBS, returning 1 if not all elements are higher. 326define i32 @test_vfchsbs_notall_bool(<4 x float> %a, <4 x float> %b) { 327; CHECK-LABEL: test_vfchsbs_notall_bool: 328; CHECK: # %bb.0: 329; CHECK-NEXT: vfchsbs %v0, %v24, %v26 330; CHECK-NEXT: lhi %r2, 0 331; CHECK-NEXT: lochinhe %r2, 1 332; CHECK-NEXT: br %r14 333 %call = call {<4 x i32>, i32} @llvm.s390.vfchsbs(<4 x float> %a, 334 <4 x float> %b) 335 %res = extractvalue {<4 x i32>, i32} %call, 1 336 %cmp = icmp sge i32 %res, 1 337 %ext = zext i1 %cmp to i32 338 ret i32 %ext 339} 340 341; VFCHSBS, storing to %ptr if not all elements are higher. 342define <4 x i32> @test_vfchsbs_notall_store(<4 x float> %a, <4 x float> %b, 343; CHECK-LABEL: test_vfchsbs_notall_store: 344; CHECK: # %bb.0: 345; CHECK-NEXT: vfchsbs %v24, %v24, %v26 346; CHECK-NEXT: ber %r14 347; CHECK-NEXT: .LBB26_1: # %store 348; CHECK-NEXT: mvhi 0(%r2), 0 349; CHECK-NEXT: br %r14 350 ptr %ptr) { 351 %call = call {<4 x i32>, i32} @llvm.s390.vfchsbs(<4 x float> %a, 352 <4 x float> %b) 353 %res = extractvalue {<4 x i32>, i32} %call, 0 354 %cc = extractvalue {<4 x i32>, i32} %call, 1 355 %cmp = icmp ugt i32 %cc, 0 356 br i1 %cmp, label %store, label %exit 357 358store: 359 store i32 0, ptr %ptr 360 br label %exit 361 362exit: 363 ret <4 x i32> %res 364} 365 366; VFCHESBS with no processing of the result. 367define i32 @test_vfchesbs(<4 x float> %a, <4 x float> %b) { 368; CHECK-LABEL: test_vfchesbs: 369; CHECK: # %bb.0: 370; CHECK-NEXT: vfchesbs %v0, %v24, %v26 371; CHECK-NEXT: ipm %r2 372; CHECK-NEXT: srl %r2, 28 373; CHECK-NEXT: br %r14 374 %call = call {<4 x i32>, i32} @llvm.s390.vfchesbs(<4 x float> %a, 375 <4 x float> %b) 376 %res = extractvalue {<4 x i32>, i32} %call, 1 377 ret i32 %res 378} 379 380; VFCHESBS, returning 1 if neither element is higher or equal. 381define i32 @test_vfchesbs_none_bool(<4 x float> %a, <4 x float> %b) { 382; CHECK-LABEL: test_vfchesbs_none_bool: 383; CHECK: # %bb.0: 384; CHECK-NEXT: vfchesbs %v0, %v24, %v26 385; CHECK-NEXT: lhi %r2, 0 386; CHECK-NEXT: lochio %r2, 1 387; CHECK-NEXT: br %r14 388 %call = call {<4 x i32>, i32} @llvm.s390.vfchesbs(<4 x float> %a, 389 <4 x float> %b) 390 %res = extractvalue {<4 x i32>, i32} %call, 1 391 %cmp = icmp eq i32 %res, 3 392 %ext = zext i1 %cmp to i32 393 ret i32 %ext 394} 395 396; VFCHESBS, storing to %ptr if neither element is higher or equal. 397define <4 x i32> @test_vfchesbs_none_store(<4 x float> %a, <4 x float> %b, 398; CHECK-LABEL: test_vfchesbs_none_store: 399; CHECK: # %bb.0: 400; CHECK-NEXT: vfchesbs %v24, %v24, %v26 401; CHECK-NEXT: bler %r14 402; CHECK-NEXT: .LBB29_1: # %store 403; CHECK-NEXT: mvhi 0(%r2), 0 404; CHECK-NEXT: br %r14 405 ptr %ptr) { 406 %call = call {<4 x i32>, i32} @llvm.s390.vfchesbs(<4 x float> %a, 407 <4 x float> %b) 408 %res = extractvalue {<4 x i32>, i32} %call, 0 409 %cc = extractvalue {<4 x i32>, i32} %call, 1 410 %cmp = icmp uge i32 %cc, 3 411 br i1 %cmp, label %store, label %exit 412 413store: 414 store i32 0, ptr %ptr 415 br label %exit 416 417exit: 418 ret <4 x i32> %res 419} 420 421; VFTCISB with the lowest useful class selector and no processing of the result. 422define i32 @test_vftcisb(<4 x float> %a) { 423; CHECK-LABEL: test_vftcisb: 424; CHECK: # %bb.0: 425; CHECK-NEXT: vftcisb %v0, %v24, 1 426; CHECK-NEXT: ipm %r2 427; CHECK-NEXT: srl %r2, 28 428; CHECK-NEXT: br %r14 429 %call = call {<4 x i32>, i32} @llvm.s390.vftcisb(<4 x float> %a, i32 1) 430 %res = extractvalue {<4 x i32>, i32} %call, 1 431 ret i32 %res 432} 433 434; VFTCISB with the highest useful class selector, returning 1 if all elements 435; have the right class (CC == 0). 436define i32 @test_vftcisb_all_bool(<4 x float> %a) { 437; CHECK-LABEL: test_vftcisb_all_bool: 438; CHECK: # %bb.0: 439; CHECK-NEXT: vftcisb %v0, %v24, 4094 440; CHECK-NEXT: lhi %r2, 0 441; CHECK-NEXT: lochie %r2, 1 442; CHECK-NEXT: br %r14 443 %call = call {<4 x i32>, i32} @llvm.s390.vftcisb(<4 x float> %a, i32 4094) 444 %res = extractvalue {<4 x i32>, i32} %call, 1 445 %cmp = icmp eq i32 %res, 0 446 %ext = zext i1 %cmp to i32 447 ret i32 %ext 448} 449 450; VFISB with a rounding mode not usable via standard intrinsics. 451define <4 x float> @test_vfisb_0_4(<4 x float> %a) { 452; CHECK-LABEL: test_vfisb_0_4: 453; CHECK: # %bb.0: 454; CHECK-NEXT: vfisb %v24, %v24, 0, 4 455; CHECK-NEXT: br %r14 456 %res = call <4 x float> @llvm.s390.vfisb(<4 x float> %a, i32 0, i32 4) 457 ret <4 x float> %res 458} 459 460; VFISB with IEEE-inexact exception suppressed. 461define <4 x float> @test_vfisb_4_0(<4 x float> %a) { 462; CHECK-LABEL: test_vfisb_4_0: 463; CHECK: # %bb.0: 464; CHECK-NEXT: vfisb %v24, %v24, 4, 0 465; CHECK-NEXT: br %r14 466 %res = call <4 x float> @llvm.s390.vfisb(<4 x float> %a, i32 4, i32 0) 467 ret <4 x float> %res 468} 469 470; VFMAXDB. 471define <2 x double> @test_vfmaxdb(<2 x double> %a, <2 x double> %b) { 472; CHECK-LABEL: test_vfmaxdb: 473; CHECK: # %bb.0: 474; CHECK-NEXT: vfmaxdb %v24, %v24, %v26, 4 475; CHECK-NEXT: br %r14 476 %res = call <2 x double> @llvm.s390.vfmaxdb(<2 x double> %a, <2 x double> %b, i32 4) 477 ret <2 x double> %res 478} 479 480; VFMINDB. 481define <2 x double> @test_vfmindb(<2 x double> %a, <2 x double> %b) { 482; CHECK-LABEL: test_vfmindb: 483; CHECK: # %bb.0: 484; CHECK-NEXT: vfmindb %v24, %v24, %v26, 4 485; CHECK-NEXT: br %r14 486 %res = call <2 x double> @llvm.s390.vfmindb(<2 x double> %a, <2 x double> %b, i32 4) 487 ret <2 x double> %res 488} 489 490; VFMAXSB. 491define <4 x float> @test_vfmaxsb(<4 x float> %a, <4 x float> %b) { 492; CHECK-LABEL: test_vfmaxsb: 493; CHECK: # %bb.0: 494; CHECK-NEXT: vfmaxsb %v24, %v24, %v26, 4 495; CHECK-NEXT: br %r14 496 %res = call <4 x float> @llvm.s390.vfmaxsb(<4 x float> %a, <4 x float> %b, i32 4) 497 ret <4 x float> %res 498} 499 500; VFMINSB. 501define <4 x float> @test_vfminsb(<4 x float> %a, <4 x float> %b) { 502; CHECK-LABEL: test_vfminsb: 503; CHECK: # %bb.0: 504; CHECK-NEXT: vfminsb %v24, %v24, %v26, 4 505; CHECK-NEXT: br %r14 506 %res = call <4 x float> @llvm.s390.vfminsb(<4 x float> %a, <4 x float> %b, i32 4) 507 ret <4 x float> %res 508} 509 510