xref: /llvm-project/llvm/test/CodeGen/SystemZ/vec-cmp-08.ll (revision e8e406041e93e50d6f8259d2793dfbd08dd43b4a) 
1; Test v1i128 comparisons.
2; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
5
6; Test eq.
7define <1 x i128> @f1(<1 x i128> %val1, <1 x i128> %val2) {
8; CHECK-LABEL: f1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vceqgs %v0, %v24, %v26
11; CHECK-NEXT:    vgbm %v24, 65535
12; CHECK-NEXT:    ber %r14
13; CHECK-NEXT:  .LBB0_1:
14; CHECK-NEXT:    vgbm %v24, 0
15; CHECK-NEXT:    br %r14
16  %cmp = icmp eq <1 x i128> %val1, %val2
17  %ret = sext <1 x i1> %cmp to <1 x i128>
18  ret <1 x i128> %ret
19}
20
21; Test ne.
22define <1 x i128> @f2(<1 x i128> %val1, <1 x i128> %val2) {
23; CHECK-LABEL: f2:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    vceqgs %v0, %v24, %v26
26; CHECK-NEXT:    vgbm %v24, 65535
27; CHECK-NEXT:    bnher %r14
28; CHECK-NEXT:  .LBB1_1:
29; CHECK-NEXT:    vgbm %v24, 0
30; CHECK-NEXT:    br %r14
31  %cmp = icmp ne <1 x i128> %val1, %val2
32  %ret = sext <1 x i1> %cmp to <1 x i128>
33  ret <1 x i128> %ret
34}
35
36; Test sgt.
37define <1 x i128> @f3(<1 x i128> %val1, <1 x i128> %val2) {
38; CHECK-LABEL: f3:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    vecg %v26, %v24
41; CHECK-NEXT:    jlh .LBB2_2
42; CHECK-NEXT:  # %bb.1:
43; CHECK-NEXT:    vchlgs %v0, %v24, %v26
44; CHECK-NEXT:  .LBB2_2:
45; CHECK-NEXT:    vgbm %v24, 65535
46; CHECK-NEXT:    blr %r14
47; CHECK-NEXT:  .LBB2_3:
48; CHECK-NEXT:    vgbm %v24, 0
49; CHECK-NEXT:    br %r14
50  %cmp = icmp sgt <1 x i128> %val1, %val2
51  %ret = sext <1 x i1> %cmp to <1 x i128>
52  ret <1 x i128> %ret
53}
54
55; Test sge.
56define <1 x i128> @f4(<1 x i128> %val1, <1 x i128> %val2) {
57; CHECK-LABEL: f4:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    vecg %v24, %v26
60; CHECK-NEXT:    jlh .LBB3_2
61; CHECK-NEXT:  # %bb.1:
62; CHECK-NEXT:    vchlgs %v0, %v26, %v24
63; CHECK-NEXT:  .LBB3_2:
64; CHECK-NEXT:    vgbm %v24, 65535
65; CHECK-NEXT:    bnlr %r14
66; CHECK-NEXT:  .LBB3_3:
67; CHECK-NEXT:    vgbm %v24, 0
68; CHECK-NEXT:    br %r14
69  %cmp = icmp sge <1 x i128> %val1, %val2
70  %ret = sext <1 x i1> %cmp to <1 x i128>
71  ret <1 x i128> %ret
72}
73
74; Test sle.
75define <1 x i128> @f5(<1 x i128> %val1, <1 x i128> %val2) {
76; CHECK-LABEL: f5:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    vecg %v26, %v24
79; CHECK-NEXT:    jlh .LBB4_2
80; CHECK-NEXT:  # %bb.1:
81; CHECK-NEXT:    vchlgs %v0, %v24, %v26
82; CHECK-NEXT:  .LBB4_2:
83; CHECK-NEXT:    vgbm %v24, 65535
84; CHECK-NEXT:    bnlr %r14
85; CHECK-NEXT:  .LBB4_3:
86; CHECK-NEXT:    vgbm %v24, 0
87; CHECK-NEXT:    br %r14
88  %cmp = icmp sle <1 x i128> %val1, %val2
89  %ret = sext <1 x i1> %cmp to <1 x i128>
90  ret <1 x i128> %ret
91}
92
93; Test slt.
94define <1 x i128> @f6(<1 x i128> %val1, <1 x i128> %val2) {
95; CHECK-LABEL: f6:
96; CHECK:       # %bb.0:
97; CHECK-NEXT:    vecg %v24, %v26
98; CHECK-NEXT:    jlh .LBB5_2
99; CHECK-NEXT:  # %bb.1:
100; CHECK-NEXT:    vchlgs %v0, %v26, %v24
101; CHECK-NEXT:  .LBB5_2:
102; CHECK-NEXT:    vgbm %v24, 65535
103; CHECK-NEXT:    blr %r14
104; CHECK-NEXT:  .LBB5_3:
105; CHECK-NEXT:    vgbm %v24, 0
106; CHECK-NEXT:    br %r14
107  %cmp = icmp slt <1 x i128> %val1, %val2
108  %ret = sext <1 x i1> %cmp to <1 x i128>
109  ret <1 x i128> %ret
110}
111
112; Test ugt.
113define <1 x i128> @f7(<1 x i128> %val1, <1 x i128> %val2) {
114; CHECK-LABEL: f7:
115; CHECK:       # %bb.0:
116; CHECK-NEXT:    veclg %v26, %v24
117; CHECK-NEXT:    jlh .LBB6_2
118; CHECK-NEXT:  # %bb.1:
119; CHECK-NEXT:    vchlgs %v0, %v24, %v26
120; CHECK-NEXT:  .LBB6_2:
121; CHECK-NEXT:    vgbm %v24, 65535
122; CHECK-NEXT:    blr %r14
123; CHECK-NEXT:  .LBB6_3:
124; CHECK-NEXT:    vgbm %v24, 0
125; CHECK-NEXT:    br %r14
126  %cmp = icmp ugt <1 x i128> %val1, %val2
127  %ret = sext <1 x i1> %cmp to <1 x i128>
128  ret <1 x i128> %ret
129}
130
131; Test uge.
132define <1 x i128> @f8(<1 x i128> %val1, <1 x i128> %val2) {
133; CHECK-LABEL: f8:
134; CHECK:       # %bb.0:
135; CHECK-NEXT:    veclg %v24, %v26
136; CHECK-NEXT:    jlh .LBB7_2
137; CHECK-NEXT:  # %bb.1:
138; CHECK-NEXT:    vchlgs %v0, %v26, %v24
139; CHECK-NEXT:  .LBB7_2:
140; CHECK-NEXT:    vgbm %v24, 65535
141; CHECK-NEXT:    bnlr %r14
142; CHECK-NEXT:  .LBB7_3:
143; CHECK-NEXT:    vgbm %v24, 0
144; CHECK-NEXT:    br %r14
145  %cmp = icmp uge <1 x i128> %val1, %val2
146  %ret = sext <1 x i1> %cmp to <1 x i128>
147  ret <1 x i128> %ret
148}
149
150; Test ule.
151define <1 x i128> @f9(<1 x i128> %val1, <1 x i128> %val2) {
152; CHECK-LABEL: f9:
153; CHECK:       # %bb.0:
154; CHECK-NEXT:    veclg %v26, %v24
155; CHECK-NEXT:    jlh .LBB8_2
156; CHECK-NEXT:  # %bb.1:
157; CHECK-NEXT:    vchlgs %v0, %v24, %v26
158; CHECK-NEXT:  .LBB8_2:
159; CHECK-NEXT:    vgbm %v24, 65535
160; CHECK-NEXT:    bnlr %r14
161; CHECK-NEXT:  .LBB8_3:
162; CHECK-NEXT:    vgbm %v24, 0
163; CHECK-NEXT:    br %r14
164  %cmp = icmp ule <1 x i128> %val1, %val2
165  %ret = sext <1 x i1> %cmp to <1 x i128>
166  ret <1 x i128> %ret
167}
168
169; Test ult.
170define <1 x i128> @f10(<1 x i128> %val1, <1 x i128> %val2) {
171; CHECK-LABEL: f10:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    veclg %v24, %v26
174; CHECK-NEXT:    jlh .LBB9_2
175; CHECK-NEXT:  # %bb.1:
176; CHECK-NEXT:    vchlgs %v0, %v26, %v24
177; CHECK-NEXT:  .LBB9_2:
178; CHECK-NEXT:    vgbm %v24, 65535
179; CHECK-NEXT:    blr %r14
180; CHECK-NEXT:  .LBB9_3:
181; CHECK-NEXT:    vgbm %v24, 0
182; CHECK-NEXT:    br %r14
183  %cmp = icmp ult <1 x i128> %val1, %val2
184  %ret = sext <1 x i1> %cmp to <1 x i128>
185  ret <1 x i128> %ret
186}
187
188; Test eq selects.
189define <1 x i128> @f11(<1 x i128> %val1, <1 x i128> %val2,
190; CHECK-LABEL: f11:
191; CHECK:       # %bb.0:
192; CHECK-NEXT:    vceqgs %v0, %v24, %v26
193; CHECK-NEXT:    je .LBB10_2
194; CHECK-NEXT:  # %bb.1:
195; CHECK-NEXT:    vlr %v28, %v30
196; CHECK-NEXT:  .LBB10_2:
197; CHECK-NEXT:    vlr %v24, %v28
198; CHECK-NEXT:    br %r14
199                       <1 x i128> %val3, <1 x i128> %val4) {
200  %cmp = icmp eq <1 x i128> %val1, %val2
201  %ret = select <1 x i1> %cmp, <1 x i128> %val3, <1 x i128> %val4
202  ret <1 x i128> %ret
203}
204
205; Test ne selects.
206define <1 x i128> @f12(<1 x i128> %val1, <1 x i128> %val2,
207; CHECK-LABEL: f12:
208; CHECK:       # %bb.0:
209; CHECK-NEXT:    vceqgs %v0, %v24, %v26
210; CHECK-NEXT:    jnhe .LBB11_2
211; CHECK-NEXT:  # %bb.1:
212; CHECK-NEXT:    vlr %v28, %v30
213; CHECK-NEXT:  .LBB11_2:
214; CHECK-NEXT:    vlr %v24, %v28
215; CHECK-NEXT:    br %r14
216                       <1 x i128> %val3, <1 x i128> %val4) {
217  %cmp = icmp ne <1 x i128> %val1, %val2
218  %ret = select <1 x i1> %cmp, <1 x i128> %val3, <1 x i128> %val4
219  ret <1 x i128> %ret
220}
221
222; Test sgt selects.
223define <1 x i128> @f13(<1 x i128> %val1, <1 x i128> %val2,
224; CHECK-LABEL: f13:
225; CHECK:       # %bb.0:
226; CHECK-NEXT:    vecg %v26, %v24
227; CHECK-NEXT:    je .LBB12_3
228; CHECK-NEXT:  # %bb.1:
229; CHECK-NEXT:    jnl .LBB12_4
230; CHECK-NEXT:  .LBB12_2:
231; CHECK-NEXT:    vlr %v24, %v28
232; CHECK-NEXT:    br %r14
233; CHECK-NEXT:  .LBB12_3:
234; CHECK-NEXT:    vchlgs %v0, %v24, %v26
235; CHECK-NEXT:    jl .LBB12_2
236; CHECK-NEXT:  .LBB12_4:
237; CHECK-NEXT:    vlr %v28, %v30
238; CHECK-NEXT:    vlr %v24, %v28
239; CHECK-NEXT:    br %r14
240                       <1 x i128> %val3, <1 x i128> %val4) {
241  %cmp = icmp sgt <1 x i128> %val1, %val2
242  %ret = select <1 x i1> %cmp, <1 x i128> %val3, <1 x i128> %val4
243  ret <1 x i128> %ret
244}
245
246; Test sge selects.
247define <1 x i128> @f14(<1 x i128> %val1, <1 x i128> %val2,
248; CHECK-LABEL: f14:
249; CHECK:       # %bb.0:
250; CHECK-NEXT:    vecg %v24, %v26
251; CHECK-NEXT:    je .LBB13_3
252; CHECK-NEXT:  # %bb.1:
253; CHECK-NEXT:    jl .LBB13_4
254; CHECK-NEXT:  .LBB13_2:
255; CHECK-NEXT:    vlr %v24, %v28
256; CHECK-NEXT:    br %r14
257; CHECK-NEXT:  .LBB13_3:
258; CHECK-NEXT:    vchlgs %v0, %v26, %v24
259; CHECK-NEXT:    jnl .LBB13_2
260; CHECK-NEXT:  .LBB13_4:
261; CHECK-NEXT:    vlr %v28, %v30
262; CHECK-NEXT:    vlr %v24, %v28
263; CHECK-NEXT:    br %r14
264                       <1 x i128> %val3, <1 x i128> %val4) {
265  %cmp = icmp sge <1 x i128> %val1, %val2
266  %ret = select <1 x i1> %cmp, <1 x i128> %val3, <1 x i128> %val4
267  ret <1 x i128> %ret
268}
269
270; Test sle selects.
271define <1 x i128> @f15(<1 x i128> %val1, <1 x i128> %val2,
272; CHECK-LABEL: f15:
273; CHECK:       # %bb.0:
274; CHECK-NEXT:    vecg %v26, %v24
275; CHECK-NEXT:    je .LBB14_3
276; CHECK-NEXT:  # %bb.1:
277; CHECK-NEXT:    jl .LBB14_4
278; CHECK-NEXT:  .LBB14_2:
279; CHECK-NEXT:    vlr %v24, %v28
280; CHECK-NEXT:    br %r14
281; CHECK-NEXT:  .LBB14_3:
282; CHECK-NEXT:    vchlgs %v0, %v24, %v26
283; CHECK-NEXT:    jnl .LBB14_2
284; CHECK-NEXT:  .LBB14_4:
285; CHECK-NEXT:    vlr %v28, %v30
286; CHECK-NEXT:    vlr %v24, %v28
287; CHECK-NEXT:    br %r14
288                       <1 x i128> %val3, <1 x i128> %val4) {
289  %cmp = icmp sle <1 x i128> %val1, %val2
290  %ret = select <1 x i1> %cmp, <1 x i128> %val3, <1 x i128> %val4
291  ret <1 x i128> %ret
292}
293
294; Test slt selects.
295define <1 x i128> @f16(<1 x i128> %val1, <1 x i128> %val2,
296; CHECK-LABEL: f16:
297; CHECK:       # %bb.0:
298; CHECK-NEXT:    vecg %v24, %v26
299; CHECK-NEXT:    je .LBB15_3
300; CHECK-NEXT:  # %bb.1:
301; CHECK-NEXT:    jnl .LBB15_4
302; CHECK-NEXT:  .LBB15_2:
303; CHECK-NEXT:    vlr %v24, %v28
304; CHECK-NEXT:    br %r14
305; CHECK-NEXT:  .LBB15_3:
306; CHECK-NEXT:    vchlgs %v0, %v26, %v24
307; CHECK-NEXT:    jl .LBB15_2
308; CHECK-NEXT:  .LBB15_4:
309; CHECK-NEXT:    vlr %v28, %v30
310; CHECK-NEXT:    vlr %v24, %v28
311; CHECK-NEXT:    br %r14
312                       <1 x i128> %val3, <1 x i128> %val4) {
313  %cmp = icmp slt <1 x i128> %val1, %val2
314  %ret = select <1 x i1> %cmp, <1 x i128> %val3, <1 x i128> %val4
315  ret <1 x i128> %ret
316}
317
318; Test ugt selects.
319define <1 x i128> @f17(<1 x i128> %val1, <1 x i128> %val2,
320; CHECK-LABEL: f17:
321; CHECK:       # %bb.0:
322; CHECK-NEXT:    veclg %v26, %v24
323; CHECK-NEXT:    je .LBB16_3
324; CHECK-NEXT:  # %bb.1:
325; CHECK-NEXT:    jnl .LBB16_4
326; CHECK-NEXT:  .LBB16_2:
327; CHECK-NEXT:    vlr %v24, %v28
328; CHECK-NEXT:    br %r14
329; CHECK-NEXT:  .LBB16_3:
330; CHECK-NEXT:    vchlgs %v0, %v24, %v26
331; CHECK-NEXT:    jl .LBB16_2
332; CHECK-NEXT:  .LBB16_4:
333; CHECK-NEXT:    vlr %v28, %v30
334; CHECK-NEXT:    vlr %v24, %v28
335; CHECK-NEXT:    br %r14
336                       <1 x i128> %val3, <1 x i128> %val4) {
337  %cmp = icmp ugt <1 x i128> %val1, %val2
338  %ret = select <1 x i1> %cmp, <1 x i128> %val3, <1 x i128> %val4
339  ret <1 x i128> %ret
340}
341
342; Test uge selects.
343define <1 x i128> @f18(<1 x i128> %val1, <1 x i128> %val2,
344; CHECK-LABEL: f18:
345; CHECK:       # %bb.0:
346; CHECK-NEXT:    veclg %v24, %v26
347; CHECK-NEXT:    je .LBB17_3
348; CHECK-NEXT:  # %bb.1:
349; CHECK-NEXT:    jl .LBB17_4
350; CHECK-NEXT:  .LBB17_2:
351; CHECK-NEXT:    vlr %v24, %v28
352; CHECK-NEXT:    br %r14
353; CHECK-NEXT:  .LBB17_3:
354; CHECK-NEXT:    vchlgs %v0, %v26, %v24
355; CHECK-NEXT:    jnl .LBB17_2
356; CHECK-NEXT:  .LBB17_4:
357; CHECK-NEXT:    vlr %v28, %v30
358; CHECK-NEXT:    vlr %v24, %v28
359; CHECK-NEXT:    br %r14
360                       <1 x i128> %val3, <1 x i128> %val4) {
361  %cmp = icmp uge <1 x i128> %val1, %val2
362  %ret = select <1 x i1> %cmp, <1 x i128> %val3, <1 x i128> %val4
363  ret <1 x i128> %ret
364}
365
366; Test ule selects.
367define <1 x i128> @f19(<1 x i128> %val1, <1 x i128> %val2,
368; CHECK-LABEL: f19:
369; CHECK:       # %bb.0:
370; CHECK-NEXT:    veclg %v26, %v24
371; CHECK-NEXT:    je .LBB18_3
372; CHECK-NEXT:  # %bb.1:
373; CHECK-NEXT:    jl .LBB18_4
374; CHECK-NEXT:  .LBB18_2:
375; CHECK-NEXT:    vlr %v24, %v28
376; CHECK-NEXT:    br %r14
377; CHECK-NEXT:  .LBB18_3:
378; CHECK-NEXT:    vchlgs %v0, %v24, %v26
379; CHECK-NEXT:    jnl .LBB18_2
380; CHECK-NEXT:  .LBB18_4:
381; CHECK-NEXT:    vlr %v28, %v30
382; CHECK-NEXT:    vlr %v24, %v28
383; CHECK-NEXT:    br %r14
384                       <1 x i128> %val3, <1 x i128> %val4) {
385  %cmp = icmp ule <1 x i128> %val1, %val2
386  %ret = select <1 x i1> %cmp, <1 x i128> %val3, <1 x i128> %val4
387  ret <1 x i128> %ret
388}
389
390; Test ult selects.
391define <1 x i128> @f20(<1 x i128> %val1, <1 x i128> %val2,
392; CHECK-LABEL: f20:
393; CHECK:       # %bb.0:
394; CHECK-NEXT:    veclg %v24, %v26
395; CHECK-NEXT:    je .LBB19_3
396; CHECK-NEXT:  # %bb.1:
397; CHECK-NEXT:    jnl .LBB19_4
398; CHECK-NEXT:  .LBB19_2:
399; CHECK-NEXT:    vlr %v24, %v28
400; CHECK-NEXT:    br %r14
401; CHECK-NEXT:  .LBB19_3:
402; CHECK-NEXT:    vchlgs %v0, %v26, %v24
403; CHECK-NEXT:    jl .LBB19_2
404; CHECK-NEXT:  .LBB19_4:
405; CHECK-NEXT:    vlr %v28, %v30
406; CHECK-NEXT:    vlr %v24, %v28
407; CHECK-NEXT:    br %r14
408                       <1 x i128> %val3, <1 x i128> %val4) {
409  %cmp = icmp ult <1 x i128> %val1, %val2
410  %ret = select <1 x i1> %cmp, <1 x i128> %val3, <1 x i128> %val4
411  ret <1 x i128> %ret
412}
413