xref: /llvm-project/llvm/test/CodeGen/SystemZ/vec-bswap-02.ll (revision 0a76f7d9d8c1fc693568ed26420c47d92a6ba0e7) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; Test stores of byte-swapped vector elements.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
5
6declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)
7declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
8declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
9
10; Test v8i16 stores.
11define void @f1(<8 x i16> %val, ptr %ptr) {
12; CHECK-LABEL: f1:
13; CHECK:       # %bb.0:
14; CHECK-NEXT:    vstbrh %v24, 0(%r2)
15; CHECK-NEXT:    br %r14
16  %swap = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %val)
17  store <8 x i16> %swap, ptr %ptr
18  ret void
19}
20
21; Test v4i32 stores.
22define void @f2(<4 x i32> %val, ptr %ptr) {
23; CHECK-LABEL: f2:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    vstbrf %v24, 0(%r2)
26; CHECK-NEXT:    br %r14
27  %swap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val)
28  store <4 x i32> %swap, ptr %ptr
29  ret void
30}
31
32; Test v2i64 stores.
33define void @f3(<2 x i64> %val, ptr %ptr) {
34; CHECK-LABEL: f3:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    vstbrg %v24, 0(%r2)
37; CHECK-NEXT:    br %r14
38  %swap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val)
39  store <2 x i64> %swap, ptr %ptr
40  ret void
41}
42
43; Test the highest aligned in-range offset.
44define void @f4(<4 x i32> %val, ptr %base) {
45; CHECK-LABEL: f4:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    vstbrf %v24, 4080(%r2)
48; CHECK-NEXT:    br %r14
49  %ptr = getelementptr <4 x i32>, ptr %base, i64 255
50  %swap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val)
51  store <4 x i32> %swap, ptr %ptr
52  ret void
53}
54
55; Test the highest unaligned in-range offset.
56define void @f5(<4 x i32> %val, ptr %base) {
57; CHECK-LABEL: f5:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    vstbrf %v24, 4095(%r2)
60; CHECK-NEXT:    br %r14
61  %addr = getelementptr i8, ptr %base, i64 4095
62  %swap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val)
63  store <4 x i32> %swap, ptr %addr, align 1
64  ret void
65}
66
67; Test the next offset up, which requires separate address logic,
68define void @f6(<4 x i32> %val, ptr %base) {
69; CHECK-LABEL: f6:
70; CHECK:       # %bb.0:
71; CHECK-NEXT:    aghi %r2, 4096
72; CHECK-NEXT:    vstbrf %v24, 0(%r2)
73; CHECK-NEXT:    br %r14
74  %ptr = getelementptr <4 x i32>, ptr %base, i64 256
75  %swap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val)
76  store <4 x i32> %swap, ptr %ptr
77  ret void
78}
79
80; Test negative offsets, which also require separate address logic,
81define void @f7(<4 x i32> %val, ptr %base) {
82; CHECK-LABEL: f7:
83; CHECK:       # %bb.0:
84; CHECK-NEXT:    aghi %r2, -16
85; CHECK-NEXT:    vstbrf %v24, 0(%r2)
86; CHECK-NEXT:    br %r14
87  %ptr = getelementptr <4 x i32>, ptr %base, i64 -1
88  %swap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val)
89  store <4 x i32> %swap, ptr %ptr
90  ret void
91}
92
93; Check that indexes are allowed.
94define void @f8(<4 x i32> %val, ptr %base, i64 %index) {
95; CHECK-LABEL: f8:
96; CHECK:       # %bb.0:
97; CHECK-NEXT:    vstbrf %v24, 0(%r3,%r2)
98; CHECK-NEXT:    br %r14
99  %addr = getelementptr i8, ptr %base, i64 %index
100  %swap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val)
101  store <4 x i32> %swap, ptr %addr, align 1
102  ret void
103}
104
105