xref: /llvm-project/llvm/test/CodeGen/SystemZ/vec-args-02.ll (revision 0a76f7d9d8c1fc693568ed26420c47d92a6ba0e7)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; Test the handling of unnamed vector arguments.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-STACK
6
7; This routine is called with two named vector argument (passed
8; in %v24 and %v26) and two unnamed vector arguments (passed
9; in the double-wide stack slots at 160 and 176).
10declare void @bar(<4 x i32>, <4 x i32>, ...)
11
12define void @foo() {
13; CHECK-VEC-LABEL: foo:
14; CHECK-VEC:       # %bb.0:
15; CHECK-VEC-NEXT:    stmg %r14, %r15, 112(%r15)
16; CHECK-VEC-NEXT:    .cfi_offset %r14, -48
17; CHECK-VEC-NEXT:    .cfi_offset %r15, -40
18; CHECK-VEC-NEXT:    aghi %r15, -192
19; CHECK-VEC-NEXT:    .cfi_def_cfa_offset 352
20; CHECK-VEC-NEXT:    vrepif %v0, 4
21; CHECK-VEC-NEXT:    vst %v0, 176(%r15), 3
22; CHECK-VEC-NEXT:    vrepif %v0, 3
23; CHECK-VEC-NEXT:    vrepif %v24, 1
24; CHECK-VEC-NEXT:    vrepif %v26, 2
25; CHECK-VEC-NEXT:    vst %v0, 160(%r15), 3
26; CHECK-VEC-NEXT:    brasl %r14, bar@PLT
27; CHECK-VEC-NEXT:    lmg %r14, %r15, 304(%r15)
28; CHECK-VEC-NEXT:    br %r14
29;
30; CHECK-STACK-LABEL: foo:
31; CHECK-STACK:       # %bb.0:
32; CHECK-STACK-NEXT:    stmg %r14, %r15, 112(%r15)
33; CHECK-STACK-NEXT:    .cfi_offset %r14, -48
34; CHECK-STACK-NEXT:    .cfi_offset %r15, -40
35; CHECK-STACK-NEXT:    aghi %r15, -192
36; CHECK-STACK-NEXT:    .cfi_def_cfa_offset 352
37; CHECK-STACK-NEXT:    vrepif %v0, 4
38; CHECK-STACK-NEXT:    vst %v0, 176(%r15), 3
39; CHECK-STACK-NEXT:    vrepif %v0, 3
40; CHECK-STACK-NEXT:    vrepif %v24, 1
41; CHECK-STACK-NEXT:    vrepif %v26, 2
42; CHECK-STACK-NEXT:    vst %v0, 160(%r15), 3
43; CHECK-STACK-NEXT:    brasl %r14, bar@PLT
44; CHECK-STACK-NEXT:    lmg %r14, %r15, 304(%r15)
45; CHECK-STACK-NEXT:    br %r14
46
47  call void (<4 x i32>, <4 x i32>, ...) @bar
48              (<4 x i32> <i32 1, i32 1, i32 1, i32 1>,
49               <4 x i32> <i32 2, i32 2, i32 2, i32 2>,
50               <4 x i32> <i32 3, i32 3, i32 3, i32 3>,
51               <4 x i32> <i32 4, i32 4, i32 4, i32 4>)
52  ret void
53}
54