xref: /llvm-project/llvm/test/CodeGen/SystemZ/vec-abs-06.ll (revision ac37755c60ba19103f08f04d07ca8f1d640153d6)
1; Test f32 and v4f32 absolute on z14.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
4
5declare float @llvm.fabs.f32(float)
6declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
7
8; Test a plain absolute.
9define <4 x float> @f1(<4 x float> %val) {
10; CHECK-LABEL: f1:
11; CHECK: vflpsb %v24, %v24
12; CHECK: br %r14
13  %ret = call <4 x float> @llvm.fabs.v4f32(<4 x float> %val)
14  ret <4 x float> %ret
15}
16
17; Test a negative absolute.
18define <4 x float> @f2(<4 x float> %val) {
19; CHECK-LABEL: f2:
20; CHECK: vflnsb %v24, %v24
21; CHECK: br %r14
22  %abs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %val)
23  %ret = fneg <4 x float> %abs
24  ret <4 x float> %ret
25}
26
27; Test an f32 absolute that uses vector registers.
28define float @f3(<4 x float> %val) {
29; CHECK-LABEL: f3:
30; CHECK: wflpsb %f0, %v24
31; CHECK: br %r14
32  %scalar = extractelement <4 x float> %val, i32 0
33  %ret = call float @llvm.fabs.f32(float %scalar)
34  ret float %ret
35}
36
37; Test an f32 negative absolute that uses vector registers.
38define float @f4(<4 x float> %val) {
39; CHECK-LABEL: f4:
40; CHECK: wflnsb %f0, %v24
41; CHECK: br %r14
42  %scalar = extractelement <4 x float> %val, i32 0
43  %abs = call float @llvm.fabs.f32(float %scalar)
44  %ret = fneg float %abs
45  ret float %ret
46}
47