1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; Test 128-bit shift right logica in vector registers on z13 3; 4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 5 6; Shift right logical immediate (general case). 7define i128 @f1(i128 %a) { 8; CHECK-LABEL: f1: 9; CHECK: # %bb.0: 10; CHECK-NEXT: vl %v0, 0(%r3), 3 11; CHECK-NEXT: vrepib %v1, 100 12; CHECK-NEXT: vsrlb %v0, %v0, %v1 13; CHECK-NEXT: vsrl %v0, %v0, %v1 14; CHECK-NEXT: vst %v0, 0(%r2), 3 15; CHECK-NEXT: br %r14 16 %res = lshr i128 %a, 100 17 ret i128 %res 18} 19 20; Shift right logical immediate (< 8 bits). 21define i128 @f2(i128 %a) { 22; CHECK-LABEL: f2: 23; CHECK: # %bb.0: 24; CHECK-NEXT: vl %v0, 0(%r3), 3 25; CHECK-NEXT: vrepib %v1, 7 26; CHECK-NEXT: vsrl %v0, %v0, %v1 27; CHECK-NEXT: vst %v0, 0(%r2), 3 28; CHECK-NEXT: br %r14 29 %res = lshr i128 %a, 7 30 ret i128 %res 31} 32 33; Shift right logical immediate (full bytes). 34define i128 @f3(i128 %a) { 35; CHECK-LABEL: f3: 36; CHECK: # %bb.0: 37; CHECK-NEXT: vl %v0, 0(%r3), 3 38; CHECK-NEXT: vrepib %v1, 32 39; CHECK-NEXT: vsrlb %v0, %v0, %v1 40; CHECK-NEXT: vst %v0, 0(%r2), 3 41; CHECK-NEXT: br %r14 42 %res = lshr i128 %a, 32 43 ret i128 %res 44} 45 46; Shift right logical variable. 47define i128 @f4(i128 %a, i128 %sh) { 48; CHECK-LABEL: f4: 49; CHECK: # %bb.0: 50; CHECK-NEXT: l %r0, 12(%r4) 51; CHECK-NEXT: vlvgp %v1, %r0, %r0 52; CHECK-NEXT: vl %v0, 0(%r3), 3 53; CHECK-NEXT: vrepb %v1, %v1, 15 54; CHECK-NEXT: vsrlb %v0, %v0, %v1 55; CHECK-NEXT: vsrl %v0, %v0, %v1 56; CHECK-NEXT: vst %v0, 0(%r2), 3 57; CHECK-NEXT: br %r14 58 %res = lshr i128 %a, %sh 59 ret i128 %res 60} 61 62; Test removal of AND mask with only bottom 7 bits set. 63define i128 @f5(i128 %a, i128 %sh) { 64; CHECK-LABEL: f5: 65; CHECK: # %bb.0: 66; CHECK-NEXT: l %r0, 12(%r4) 67; CHECK-NEXT: vlvgp %v1, %r0, %r0 68; CHECK-NEXT: vl %v0, 0(%r3), 3 69; CHECK-NEXT: vrepb %v1, %v1, 15 70; CHECK-NEXT: vsrlb %v0, %v0, %v1 71; CHECK-NEXT: vsrl %v0, %v0, %v1 72; CHECK-NEXT: vst %v0, 0(%r2), 3 73; CHECK-NEXT: br %r14 74 %and = and i128 %sh, 127 75 %shift = lshr i128 %a, %and 76 ret i128 %shift 77} 78 79; Test removal of AND mask including but not limited to bottom 7 bits. 80define i128 @f6(i128 %a, i128 %sh) { 81; CHECK-LABEL: f6: 82; CHECK: # %bb.0: 83; CHECK-NEXT: l %r0, 12(%r4) 84; CHECK-NEXT: vlvgp %v1, %r0, %r0 85; CHECK-NEXT: vl %v0, 0(%r3), 3 86; CHECK-NEXT: vrepb %v1, %v1, 15 87; CHECK-NEXT: vsrlb %v0, %v0, %v1 88; CHECK-NEXT: vsrl %v0, %v0, %v1 89; CHECK-NEXT: vst %v0, 0(%r2), 3 90; CHECK-NEXT: br %r14 91 %and = and i128 %sh, 511 92 %shift = lshr i128 %a, %and 93 ret i128 %shift 94} 95 96; Test that AND is not removed when some lower 7 bits are not set. 97define i128 @f7(i128 %a, i128 %sh) { 98; CHECK-LABEL: f7: 99; CHECK: # %bb.0: 100; CHECK-NEXT: lhi %r0, 63 101; CHECK-NEXT: n %r0, 12(%r4) 102; CHECK-NEXT: vlvgp %v1, %r0, %r0 103; CHECK-NEXT: vl %v0, 0(%r3), 3 104; CHECK-NEXT: vrepb %v1, %v1, 15 105; CHECK-NEXT: vsrlb %v0, %v0, %v1 106; CHECK-NEXT: vsrl %v0, %v0, %v1 107; CHECK-NEXT: vst %v0, 0(%r2), 3 108; CHECK-NEXT: br %r14 109 %and = and i128 %sh, 63 110 %shift = lshr i128 %a, %and 111 ret i128 %shift 112} 113 114; Test that AND with two register operands is not affected. 115define i128 @f8(i128 %a, i128 %b, i128 %sh) { 116; CHECK-LABEL: f8: 117; CHECK: # %bb.0: 118; CHECK-NEXT: vl %v1, 0(%r4), 3 119; CHECK-NEXT: vl %v2, 0(%r5), 3 120; CHECK-NEXT: vn %v1, %v2, %v1 121; CHECK-NEXT: vlgvf %r0, %v1, 3 122; CHECK-NEXT: vlvgp %v1, %r0, %r0 123; CHECK-NEXT: vl %v0, 0(%r3), 3 124; CHECK-NEXT: vrepb %v1, %v1, 15 125; CHECK-NEXT: vsrlb %v0, %v0, %v1 126; CHECK-NEXT: vsrl %v0, %v0, %v1 127; CHECK-NEXT: vst %v0, 0(%r2), 3 128; CHECK-NEXT: br %r14 129 %and = and i128 %sh, %b 130 %shift = lshr i128 %a, %and 131 ret i128 %shift 132} 133 134; Test that AND is not entirely removed if the result is reused. 135define i128 @f9(i128 %a, i128 %sh) { 136; CHECK-LABEL: f9: 137; CHECK: # %bb.0: 138; CHECK-NEXT: larl %r1, .LCPI8_0 139; CHECK-NEXT: vl %v1, 0(%r4), 3 140; CHECK-NEXT: vl %v2, 0(%r1), 3 141; CHECK-NEXT: vn %v1, %v1, %v2 142; CHECK-NEXT: vlgvf %r0, %v1, 3 143; CHECK-NEXT: vlvgp %v2, %r0, %r0 144; CHECK-NEXT: vl %v0, 0(%r3), 3 145; CHECK-NEXT: vrepb %v2, %v2, 15 146; CHECK-NEXT: vsrlb %v0, %v0, %v2 147; CHECK-NEXT: vsrl %v0, %v0, %v2 148; CHECK-NEXT: vaq %v0, %v1, %v0 149; CHECK-NEXT: vst %v0, 0(%r2), 3 150; CHECK-NEXT: br %r14 151 %and = and i128 %sh, 127 152 %shift = lshr i128 %a, %and 153 %reuse = add i128 %and, %shift 154 ret i128 %reuse 155} 156 157