xref: /llvm-project/llvm/test/CodeGen/SystemZ/scalar-cttz-01.ll (revision a65ccc1b9fe740c9f65d9cf2b627de50278aad56) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
3
4declare i64 @llvm.cttz.i64(i64, i1)
5declare i32 @llvm.cttz.i32(i32, i1)
6declare i16 @llvm.cttz.i16(i16, i1)
7declare i8 @llvm.cttz.i8(i8, i1)
8
9define i64 @f0(i64 %arg) {
10; CHECK-LABEL: f0:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    lay %r0, -1(%r2)
13; CHECK-NEXT:    ngr %r2, %r0
14; CHECK-NEXT:    xgr %r2, %r0
15; CHECK-NEXT:    flogr %r0, %r2
16; CHECK-NEXT:    lghi %r2, 64
17; CHECK-NEXT:    sgr %r2, %r0
18; CHECK-NEXT:    br %r14
19  %1 = tail call i64 @llvm.cttz.i64(i64 %arg, i1 false)
20  ret i64 %1
21}
22
23define i64 @f1(i64 %arg) {
24; CHECK-LABEL: f1:
25; CHECK:       # %bb.0:
26; CHECK-NEXT:    lay %r0, -1(%r2)
27; CHECK-NEXT:    ngr %r2, %r0
28; CHECK-NEXT:    xgr %r2, %r0
29; CHECK-NEXT:    flogr %r0, %r2
30; CHECK-NEXT:    lghi %r2, 64
31; CHECK-NEXT:    sgr %r2, %r0
32; CHECK-NEXT:    br %r14
33  %1 = tail call i64 @llvm.cttz.i64(i64 %arg, i1 true)
34  ret i64 %1
35}
36
37define i32 @f2(i32 %arg) {
38; CHECK-LABEL: f2:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    ahik %r0, %r2, -1
41; CHECK-NEXT:    xilf %r2, 4294967295
42; CHECK-NEXT:    nr %r0, %r2
43; CHECK-NEXT:    popcnt %r0, %r0
44; CHECK-NEXT:    sllk %r1, %r0, 16
45; CHECK-NEXT:    ar %r0, %r1
46; CHECK-NEXT:    sllk %r1, %r0, 8
47; CHECK-NEXT:    ar %r0, %r1
48; CHECK-NEXT:    srlk %r2, %r0, 24
49; CHECK-NEXT:    br %r14
50  %1 = tail call i32 @llvm.cttz.i32(i32 %arg, i1 false)
51  ret i32 %1
52}
53
54define i32 @f3(i32 %arg) {
55; CHECK-LABEL: f3:
56; CHECK:       # %bb.0:
57; CHECK-NEXT:    ahik %r0, %r2, -1
58; CHECK-NEXT:    xilf %r2, 4294967295
59; CHECK-NEXT:    nr %r0, %r2
60; CHECK-NEXT:    popcnt %r0, %r0
61; CHECK-NEXT:    sllk %r1, %r0, 16
62; CHECK-NEXT:    ar %r0, %r1
63; CHECK-NEXT:    sllk %r1, %r0, 8
64; CHECK-NEXT:    ar %r0, %r1
65; CHECK-NEXT:    srlk %r2, %r0, 24
66; CHECK-NEXT:    br %r14
67  %1 = tail call i32 @llvm.cttz.i32(i32 %arg, i1 true)
68  ret i32 %1
69}
70
71define i16 @f4(i16 %arg) {
72; CHECK-LABEL: f4:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    ahik %r0, %r2, -1
75; CHECK-NEXT:    xilf %r2, 4294967295
76; CHECK-NEXT:    nr %r0, %r2
77; CHECK-NEXT:    llhr %r0, %r0
78; CHECK-NEXT:    popcnt %r0, %r0
79; CHECK-NEXT:    risblg %r1, %r0, 16, 151, 8
80; CHECK-NEXT:    ar %r0, %r1
81; CHECK-NEXT:    srlk %r2, %r0, 8
82; CHECK-NEXT:    br %r14
83  %1 = tail call i16 @llvm.cttz.i16(i16 %arg, i1 false)
84  ret i16 %1
85}
86
87define i16 @f5(i16 %arg) {
88; CHECK-LABEL: f5:
89; CHECK:       # %bb.0:
90; CHECK-NEXT:    ahik %r0, %r2, -1
91; CHECK-NEXT:    xilf %r2, 4294967295
92; CHECK-NEXT:    nr %r0, %r2
93; CHECK-NEXT:    llhr %r0, %r0
94; CHECK-NEXT:    popcnt %r0, %r0
95; CHECK-NEXT:    risblg %r1, %r0, 16, 151, 8
96; CHECK-NEXT:    ar %r0, %r1
97; CHECK-NEXT:    srlk %r2, %r0, 8
98; CHECK-NEXT:    br %r14
99  %1 = tail call i16 @llvm.cttz.i16(i16 %arg, i1 true)
100  ret i16 %1
101}
102
103define i8 @f6(i8 %arg) {
104; CHECK-LABEL: f6:
105; CHECK:       # %bb.0:
106; CHECK-NEXT:    ahik %r0, %r2, -1
107; CHECK-NEXT:    xilf %r2, 4294967295
108; CHECK-NEXT:    nr %r0, %r2
109; CHECK-NEXT:    llcr %r0, %r0
110; CHECK-NEXT:    popcnt %r2, %r0
111; CHECK-NEXT:    # kill: def $r2l killed $r2l killed $r2d
112; CHECK-NEXT:    br %r14
113  %1 = tail call i8 @llvm.cttz.i8(i8 %arg, i1 false)
114  ret i8 %1
115}
116
117define i8 @f7(i8 %arg) {
118; CHECK-LABEL: f7:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    ahik %r0, %r2, -1
121; CHECK-NEXT:    xilf %r2, 4294967295
122; CHECK-NEXT:    nr %r0, %r2
123; CHECK-NEXT:    llcr %r0, %r0
124; CHECK-NEXT:    popcnt %r2, %r0
125; CHECK-NEXT:    # kill: def $r2l killed $r2l killed $r2d
126; CHECK-NEXT:    br %r14
127  %1 = tail call i8 @llvm.cttz.i8(i8 %arg, i1 true)
128  ret i8 %1
129}
130