1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple s390x-ibm-linux -mcpu=z13 -systemz-subreg-liveness -verify-machineinstrs -start-before register-coalescer -stop-after greedy -o - %s | FileCheck %s 3 4# Check that when we split the live-range with several active lanes 5# as part of the live-range update, we correctly eliminate the VNI from 6# the relevant part. 7# 8# In this specific test, the register coalescer will: 9# 1. Merge %0 with %1, creating a live-range for the full value subreg_l32 + subreg_h32 10# (actually %0 gets merge with %1 via rematerialization, and technically %0 and %1 11# remain two different live-ranges.) 12# 2. Merge %2 with %1 triggering a split into the subreg_l32 + subreg_h32 ranges, since 13# %2 only touches subreg_l32. As part of the split the subrange covering subreg_h32 14# must contain only the VNI for the high part (i.e., the one tied with the remaaat of %0). 15# This used to be broken and trigger a machine verifier error, because we were not 16# clearing the dead value w.r.t. lanes when doing the splitting. I.e., we were ending 17# with a subrange referring a value that did not define that lane. 18# 19# PR40835 20--- 21name: main 22tracksRegLiveness: true 23body: | 24 bb.0: 25 26 ; CHECK-LABEL: name: main 27 ; CHECK: [[LGHI:%[0-9]+]]:gr64bit = LGHI 43 28 ; CHECK-NEXT: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 43 29 ; CHECK-NEXT: undef [[LGHI1:%[0-9]+]].subreg_l32:gr64bit = MSR [[LGHI1]].subreg_l32, [[LGHI1]].subreg_l32 30 ; CHECK-NEXT: [[LGHI1:%[0-9]+]].subreg_l32:gr64bit = AHIMux [[LGHI1]].subreg_l32, 9, implicit-def dead $cc 31 ; CHECK-NEXT: undef [[LGFI:%[0-9]+]].subreg_l64:gr128bit = LGFI -245143785, implicit [[LGHI1]].subreg_l32 32 ; CHECK-NEXT: [[LGFI:%[0-9]+]]:gr128bit = DLGR [[LGFI]], [[LGHI]] 33 ; CHECK-NEXT: Return implicit [[LGFI]] 34 %0:gr64bit = LGHI 43 35 %1:gr32bit = COPY %0.subreg_l32 36 %1:gr32bit = MSR %1, %1 37 %2:gr32bit = COPY killed %1 38 %2:gr32bit = AHIMux killed %2, 9, implicit-def dead $cc 39 undef %3.subreg_l64:gr128bit = LGFI -245143785, implicit killed %2 40 %3:gr128bit = DLGR %3:gr128bit, killed %0 41 Return implicit killed %3 42 43... 44 45# Make sure the compiler does not choke on VNIs that don't 46# an explicit MI as definition. 47# In that specific example, this is the PHI not explicitly 48# represented for the value carried by %7. 49--- 50name: segfault 51tracksRegLiveness: true 52frameInfo: 53 adjustsStack: true 54liveins: [] 55body: | 56 ; CHECK-LABEL: name: segfault 57 ; CHECK: bb.0: 58 ; CHECK-NEXT: successors: %bb.1(0x80000000) 59 ; CHECK-NEXT: {{ $}} 60 ; CHECK-NEXT: [[LGHI:%[0-9]+]]:addr64bit = LGHI 0 61 ; CHECK-NEXT: {{ $}} 62 ; CHECK-NEXT: bb.1: 63 ; CHECK-NEXT: successors: %bb.1(0x80000000) 64 ; CHECK-NEXT: {{ $}} 65 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0 66 ; CHECK-NEXT: [[LGFR:%[0-9]+]]:gr64bit = LGFR [[LGHI]].subreg_l32 67 ; CHECK-NEXT: $r2d = LGHI 123 68 ; CHECK-NEXT: $r3d = LGHI 0 69 ; CHECK-NEXT: $r4d = LGHI 0 70 ; CHECK-NEXT: $r5d = COPY [[LGFR]] 71 ; CHECK-NEXT: KILL killed $r2d, killed $r3d, killed $r4d, $r5d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc 72 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0 73 ; CHECK-NEXT: [[LGHI:%[0-9]+]]:addr64bit = nuw nsw LA [[LGHI]], 1, $noreg 74 ; CHECK-NEXT: J %bb.1 75 bb.0: 76 successors: %bb.1(0x80000000) 77 78 %2:gr64bit = LGHI 0 79 %5:gr64bit = LGHI 123 80 %7:addr64bit = COPY %2 81 82 bb.1: 83 successors: %bb.1(0x80000000) 84 85 %0:addr64bit = COPY killed %7 86 ADJCALLSTACKDOWN 0, 0 87 %3:gr32bit = COPY %0.subreg_l32 88 %4:gr64bit = LGFR killed %3 89 $r2d = COPY %5 90 $r3d = COPY %2 91 $r4d = COPY %2 92 $r5d = COPY killed %4 93 KILL killed $r2d, killed $r3d, killed $r4d, killed $r5d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc 94 ADJCALLSTACKUP 0, 0 95 %1:gr64bit = nuw nsw LA killed %0, 1, $noreg 96 %7:addr64bit = COPY killed %1 97 J %bb.1 98 99... 100