1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; Test 128-bit OR-NOT in vector registers on z14 3; 4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s 5 6; Or with complement. 7define i128 @f1(i128 %a, i128 %b) { 8; CHECK-LABEL: f1: 9; CHECK: # %bb.0: 10; CHECK-NEXT: vl %v0, 0(%r4), 3 11; CHECK-NEXT: vl %v1, 0(%r3), 3 12; CHECK-NEXT: voc %v0, %v1, %v0 13; CHECK-NEXT: vst %v0, 0(%r2), 3 14; CHECK-NEXT: br %r14 15 %notb = xor i128 %b, -1 16 %res = or i128 %a, %notb 17 ret i128 %res 18} 19