xref: /llvm-project/llvm/test/CodeGen/SystemZ/memmem-exrl-cc.mir (revision 655f0fc4b96d02b1baa075a0bbd8dda936070796) 
1# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 -O3 -start-before=finalize-isel %s -o - \
2# RUN:   -verify-machineinstrs | FileCheck %s
3#
4# Test that the exrl used for the remainder of a memset (after xc loop) is
5# not rescheduled incorrectly in a way that interfers with CC liveness.
6
7--- |
8  define void @fun(ptr %Src, ptr %Dst, i64 %Len) { ret void }
9...
10
11# CHECK-LABEL: fun:
12
13# CHECK:       exrl    %r4, .Ltmp0
14# CHECK-NEXT:  cgije
15
16# CHECK:       exrl    %r4, .Ltmp1
17# CHECK-NEXT:  tmll
18# CHECK-NEXT:  jne
19
20# CHECK:       .Ltmp1:
21# CHECK-NEXT:  xc      0(1,%r3), 0(%r2)
22# CHECK-NEXT:  .Ltmp0:
23# CHECK-NEXT:  xc      0(1,%r14), 0(%r14)
24---
25name:            fun
26alignment:       16
27tracksRegLiveness: true
28registers:
29  - { id: 0, class: grx32bit }
30  - { id: 1, class: addr64bit }
31  - { id: 2, class: addr64bit }
32  - { id: 3, class: gr64bit }
33  - { id: 4, class: gr64bit }
34  - { id: 5, class: grx32bit }
35  - { id: 6, class: addr64bit }
36  - { id: 7, class: addr64bit }
37  - { id: 8, class: gr64bit }
38  - { id: 9, class: gr128bit }
39  - { id: 10, class: gr64bit }
40  - { id: 11, class: gr32bit }
41  - { id: 12, class: gr32bit }
42  - { id: 13, class: gr32bit }
43  - { id: 14, class: addr64bit }
44  - { id: 15, class: gr64bit }
45  - { id: 16, class: gr64bit }
46  - { id: 17, class: addr64bit }
47  - { id: 18, class: gr64bit }
48  - { id: 19, class: vr128bit }
49liveins:
50  - { reg: '$r2d', virtual-reg: '%1' }
51  - { reg: '$r3d', virtual-reg: '%2' }
52  - { reg: '$r4d', virtual-reg: '%3' }
53frameInfo:
54  maxAlignment:    1
55machineFunctionInfo: {}
56jumpTable:
57  kind:            block-address
58  entries:
59    - id:              0
60      blocks:          [ '%bb.1', '%bb.2', '%bb.5', '%bb.6', '%bb.7', '%bb.7',
61                         '%bb.7', '%bb.7', '%bb.7', '%bb.7', '%bb.7', '%bb.7',
62                         '%bb.2', '%bb.5', '%bb.6', '%bb.7', '%bb.1', '%bb.2',
63                         '%bb.7', '%bb.7', '%bb.5' ]
64body:             |
65  bb.0:
66    liveins: $r2d, $r3d, $r4d
67
68    %3:gr64bit = COPY $r4d
69    %2:addr64bit = COPY $r3d
70    %1:addr64bit = COPY $r2d
71    %4:gr64bit = LGHI 0
72
73  bb.8:
74    successors: %bb.1(0x00000000), %bb.2(0x00000000), %bb.5(0x00000000), %bb.6(0x00000000), %bb.7(0x80000000)
75
76    %6:addr64bit = SLLG %4, $noreg, 3
77    %7:addr64bit = LARL %jump-table.0
78    BI killed %6, 0, killed %7 :: (load (s64) from jump-table)
79
80  bb.1:
81    successors:
82
83
84  bb.2:
85    successors: %bb.4(0x30000000), %bb.3(0x50000000)
86
87    %8:gr64bit = LG %1, 0, $noreg
88    %9:gr128bit = FLOGR killed %8, implicit-def dead $cc
89    %10:gr64bit = COPY %9.subreg_h64
90    %11:gr32bit = COPY %10.subreg_l32
91    %12:gr32bit = LHIMux 64
92    %13:gr32bit = nuw nsw SRK killed %12, killed %11, implicit-def dead $cc
93    %0:grx32bit = COPY %13
94    %14:addr64bit = AGHIK %3, -1, implicit-def dead $cc
95    XCReg %1, 0, %1, 0, %14, implicit-def dead $cc
96    XCReg %2, 0, %1, 0, %14, implicit-def dead $cc
97    TMLMux %13, 7, implicit-def $cc
98    BRC 15, 8, %bb.4, implicit $cc
99    J %bb.3
100
101  bb.3:
102    successors:
103
104    %16:gr64bit = IMPLICIT_DEF
105    %15:gr64bit = INSERT_SUBREG %16, %0, %subreg.subreg_l32
106    %18:gr64bit = IMPLICIT_DEF
107    %17:addr64bit = RISBGN %18, killed %15, 54, 185, 3
108    %19:vr128bit = VGBM 0
109    VST killed %19, killed %17, 16, $noreg
110
111  bb.4:
112    successors:
113
114
115  bb.5:
116    successors:
117
118
119  bb.6:
120    successors:
121
122
123  bb.7:
124    Return
125
126...
127