xref: /llvm-project/llvm/test/CodeGen/SystemZ/int-cmp-64.ll (revision 8424bf207efd89eacf2fe893b67be98d535e1db6) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; Test 128-bit comparisons in vector registers on arch15
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 -verify-machineinstrs | FileCheck %s
5
6; Equality comparison.
7define i64 @f1(i128 %value1, i128 %value2, i64 %a, i64 %b) {
8; CHECK-LABEL: f1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vl %v0, 0(%r3), 3
11; CHECK-NEXT:    vl %v1, 0(%r2), 3
12; CHECK-NEXT:    vecq %v1, %v0
13; CHECK-NEXT:    selgre %r2, %r4, %r5
14; CHECK-NEXT:    br %r14
15  %cond = icmp eq i128 %value1, %value2
16  %res = select i1 %cond, i64 %a, i64 %b
17  ret i64 %res
18}
19
20; Inequality comparison.
21define i64 @f2(i128 %value1, i128 %value2, i64 %a, i64 %b) {
22; CHECK-LABEL: f2:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    vl %v0, 0(%r3), 3
25; CHECK-NEXT:    vl %v1, 0(%r2), 3
26; CHECK-NEXT:    vecq %v1, %v0
27; CHECK-NEXT:    selgrlh %r2, %r4, %r5
28; CHECK-NEXT:    br %r14
29  %cond = icmp ne i128 %value1, %value2
30  %res = select i1 %cond, i64 %a, i64 %b
31  ret i64 %res
32}
33
34; Signed greater-than comparison.
35define i64 @f3(i128 %value1, i128 %value2, i64 %a, i64 %b) {
36; CHECK-LABEL: f3:
37; CHECK:       # %bb.0:
38; CHECK-NEXT:    vl %v0, 0(%r3), 3
39; CHECK-NEXT:    vl %v1, 0(%r2), 3
40; CHECK-NEXT:    vecq %v1, %v0
41; CHECK-NEXT:    selgrh %r2, %r4, %r5
42; CHECK-NEXT:    br %r14
43  %cond = icmp sgt i128 %value1, %value2
44  %res = select i1 %cond, i64 %a, i64 %b
45  ret i64 %res
46}
47
48; Signed less-than comparison.
49define i64 @f4(i128 %value1, i128 %value2, i64 %a, i64 %b) {
50; CHECK-LABEL: f4:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    vl %v0, 0(%r3), 3
53; CHECK-NEXT:    vl %v1, 0(%r2), 3
54; CHECK-NEXT:    vecq %v1, %v0
55; CHECK-NEXT:    selgrl %r2, %r4, %r5
56; CHECK-NEXT:    br %r14
57  %cond = icmp slt i128 %value1, %value2
58  %res = select i1 %cond, i64 %a, i64 %b
59  ret i64 %res
60}
61
62; Signed greater-or-equal comparison.
63define i64 @f5(i128 %value1, i128 %value2, i64 %a, i64 %b) {
64; CHECK-LABEL: f5:
65; CHECK:       # %bb.0:
66; CHECK-NEXT:    vl %v0, 0(%r3), 3
67; CHECK-NEXT:    vl %v1, 0(%r2), 3
68; CHECK-NEXT:    vecq %v1, %v0
69; CHECK-NEXT:    selgrhe %r2, %r4, %r5
70; CHECK-NEXT:    br %r14
71  %cond = icmp sge i128 %value1, %value2
72  %res = select i1 %cond, i64 %a, i64 %b
73  ret i64 %res
74}
75
76; Signed less-or-equal comparison.
77define i64 @f6(i128 %value1, i128 %value2, i64 %a, i64 %b) {
78; CHECK-LABEL: f6:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    vl %v0, 0(%r3), 3
81; CHECK-NEXT:    vl %v1, 0(%r2), 3
82; CHECK-NEXT:    vecq %v1, %v0
83; CHECK-NEXT:    selgrle %r2, %r4, %r5
84; CHECK-NEXT:    br %r14
85  %cond = icmp sle i128 %value1, %value2
86  %res = select i1 %cond, i64 %a, i64 %b
87  ret i64 %res
88}
89
90; Unsigned greater-than comparison.
91define i64 @f7(i128 %value1, i128 %value2, i64 %a, i64 %b) {
92; CHECK-LABEL: f7:
93; CHECK:       # %bb.0:
94; CHECK-NEXT:    vl %v0, 0(%r3), 3
95; CHECK-NEXT:    vl %v1, 0(%r2), 3
96; CHECK-NEXT:    veclq %v1, %v0
97; CHECK-NEXT:    selgrh %r2, %r4, %r5
98; CHECK-NEXT:    br %r14
99  %cond = icmp ugt i128 %value1, %value2
100  %res = select i1 %cond, i64 %a, i64 %b
101  ret i64 %res
102}
103
104; Unsigned less-than comparison.
105define i64 @f8(i128 %value1, i128 %value2, i64 %a, i64 %b) {
106; CHECK-LABEL: f8:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    vl %v0, 0(%r3), 3
109; CHECK-NEXT:    vl %v1, 0(%r2), 3
110; CHECK-NEXT:    veclq %v1, %v0
111; CHECK-NEXT:    selgrl %r2, %r4, %r5
112; CHECK-NEXT:    br %r14
113  %cond = icmp ult i128 %value1, %value2
114  %res = select i1 %cond, i64 %a, i64 %b
115  ret i64 %res
116}
117
118; Unsigned greater-or-equal comparison.
119define i64 @f9(i128 %value1, i128 %value2, i64 %a, i64 %b) {
120; CHECK-LABEL: f9:
121; CHECK:       # %bb.0:
122; CHECK-NEXT:    vl %v0, 0(%r3), 3
123; CHECK-NEXT:    vl %v1, 0(%r2), 3
124; CHECK-NEXT:    veclq %v1, %v0
125; CHECK-NEXT:    selgrhe %r2, %r4, %r5
126; CHECK-NEXT:    br %r14
127  %cond = icmp uge i128 %value1, %value2
128  %res = select i1 %cond, i64 %a, i64 %b
129  ret i64 %res
130}
131
132; Unsigned less-or-equal comparison.
133define i64 @f10(i128 %value1, i128 %value2, i64 %a, i64 %b) {
134; CHECK-LABEL: f10:
135; CHECK:       # %bb.0:
136; CHECK-NEXT:    vl %v0, 0(%r3), 3
137; CHECK-NEXT:    vl %v1, 0(%r2), 3
138; CHECK-NEXT:    veclq %v1, %v0
139; CHECK-NEXT:    selgrle %r2, %r4, %r5
140; CHECK-NEXT:    br %r14
141  %cond = icmp ule i128 %value1, %value2
142  %res = select i1 %cond, i64 %a, i64 %b
143  ret i64 %res
144}
145
146; Select between i128 values.
147define i128 @f11(i64 %value1, i64 %value2, i128 %a, i128 %b) {
148; CHECK-LABEL: f11:
149; CHECK:       # %bb.0:
150; CHECK-NEXT:    vl %v0, 0(%r5), 3
151; CHECK-NEXT:    cgrje %r3, %r4, .LBB10_2
152; CHECK-NEXT:  # %bb.1:
153; CHECK-NEXT:    vl %v1, 0(%r6), 3
154; CHECK-NEXT:    vaq %v0, %v0, %v1
155; CHECK-NEXT:  .LBB10_2:
156; CHECK-NEXT:    vst %v0, 0(%r2), 3
157; CHECK-NEXT:    br %r14
158  %cond = icmp eq i64 %value1, %value2
159  %sum = add i128 %a, %b
160  %res = select i1 %cond, i128 %a, i128 %sum
161  ret i128 %res
162}
163