1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 < %s | FileCheck %s --check-prefixes=CHECK,Z15 3; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s --check-prefixes=CHECK,Z13 4; 5; Test inline assembly where the operand is bitcasted. 6 7define signext i32 @int_and_f(i32 signext %cc_dep1) { 8; CHECK-LABEL: int_and_f: 9; CHECK: # %bb.0: # %entry 10; CHECK-NEXT: vlvgf %v0, %r2, 0 11; CHECK-NEXT: #APP 12; CHECK-NEXT: #NO_APP 13; CHECK-NEXT: vlgvf %r0, %v0, 0 14; CHECK-NEXT: lgfr %r2, %r0 15; CHECK-NEXT: br %r14 16entry: 17 %0 = tail call i32 asm sideeffect "", "={f0},0"(i32 %cc_dep1) 18 ret i32 %0 19} 20 21define i64 @long_and_f(i64 %cc_dep1) { 22; CHECK-LABEL: long_and_f: 23; CHECK: # %bb.0: # %entry 24; CHECK-NEXT: ldgr %f1, %r2 25; CHECK-NEXT: #APP 26; CHECK-NEXT: #NO_APP 27; CHECK-NEXT: lgdr %r2, %f1 28; CHECK-NEXT: br %r14 29entry: 30 %0 = tail call i64 asm sideeffect "", "={f1},0"(i64 %cc_dep1) 31 ret i64 %0 32} 33 34define void @__int128_and_f(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) { 35; Z15-LABEL: __int128_and_f: 36; Z15: # %bb.0: # %entry 37; Z15-NEXT: vl %v0, 0(%r3), 3 38; Z15-NEXT: vlr %v4, %v0 39; Z15-NEXT: vrepg %v6, %v0, 1 40; Z15-NEXT: #APP 41; Z15-NEXT: #NO_APP 42; Z15-NEXT: vmrhg %v0, %v4, %v6 43; Z15-NEXT: vst %v0, 0(%r2), 3 44; Z15-NEXT: br %r14 45; 46; Z13-LABEL: __int128_and_f: 47; Z13: # %bb.0: # %entry 48; Z13-NEXT: ld %f4, 0(%r3) 49; Z13-NEXT: ld %f6, 8(%r3) 50; Z13-NEXT: #APP 51; Z13-NEXT: #NO_APP 52; Z13-NEXT: std %f4, 0(%r2) 53; Z13-NEXT: std %f6, 8(%r2) 54; Z13-NEXT: br %r14 55entry: 56 %cc_dep1 = load i128, ptr %0, align 8 57 %1 = tail call i128 asm sideeffect "", "={f4},0"(i128 %cc_dep1) 58 store i128 %1, ptr %agg.result, align 8 59 ret void 60} 61 62define signext i32 @int_and_v(i32 signext %cc_dep1) { 63; CHECK-LABEL: int_and_v: 64; CHECK: # %bb.0: # %entry 65; CHECK-NEXT: vlvgf %v0, %r2, 0 66; CHECK-NEXT: #APP 67; CHECK-NEXT: #NO_APP 68; CHECK-NEXT: vlgvf %r0, %v0, 0 69; CHECK-NEXT: lgfr %r2, %r0 70; CHECK-NEXT: br %r14 71entry: 72 %0 = tail call i32 asm sideeffect "", "={v0},0"(i32 %cc_dep1) 73 ret i32 %0 74} 75 76define i64 @long_and_v(i64 %cc_dep1) { 77; CHECK-LABEL: long_and_v: 78; CHECK: # %bb.0: # %entry 79; CHECK-NEXT: ldgr %f1, %r2 80; CHECK-NEXT: #APP 81; CHECK-NEXT: #NO_APP 82; CHECK-NEXT: lgdr %r2, %f1 83; CHECK-NEXT: br %r14 84entry: 85 %0 = tail call i64 asm sideeffect "", "={v1},0"(i64 %cc_dep1) 86 ret i64 %0 87} 88 89define void @__int128_and_v(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) { 90; CHECK-LABEL: __int128_and_v: 91; CHECK: # %bb.0: # %entry 92; CHECK-NEXT: vl %v2, 0(%r3), 3 93; CHECK-NEXT: #APP 94; CHECK-NEXT: #NO_APP 95; CHECK-NEXT: vst %v2, 0(%r2), 3 96; CHECK-NEXT: br %r14 97entry: 98 %cc_dep1 = load i128, ptr %0, align 8 99 %1 = tail call i128 asm sideeffect "", "={v2},0"(i128 %cc_dep1) 100 store i128 %1, ptr %agg.result, align 8 101 ret void 102} 103 104define float @float_and_r(float %cc_dep1) { 105; CHECK-LABEL: float_and_r: 106; CHECK: # %bb.0: # %entry 107; CHECK-NEXT: vlgvf %r0, %v0, 0 108; CHECK-NEXT: # kill: def $r0l killed $r0l killed $r0d 109; CHECK-NEXT: #APP 110; CHECK-NEXT: #NO_APP 111; CHECK-NEXT: vlvgf %v0, %r0, 0 112; CHECK-NEXT: br %r14 113entry: 114 %0 = tail call float asm sideeffect "", "={r0},0"(float %cc_dep1) 115 ret float %0 116} 117 118define double @double_and_r(double %cc_dep1) { 119; CHECK-LABEL: double_and_r: 120; CHECK: # %bb.0: # %entry 121; CHECK-NEXT: lgdr %r1, %f0 122; CHECK-NEXT: #APP 123; CHECK-NEXT: #NO_APP 124; CHECK-NEXT: ldgr %f0, %r1 125; CHECK-NEXT: br %r14 126entry: 127 %0 = tail call double asm sideeffect "", "={r1},0"(double %cc_dep1) 128 ret double %0 129} 130 131define void @longdouble_and_r(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) { 132; CHECK-LABEL: longdouble_and_r: 133; CHECK: # %bb.0: # %entry 134; CHECK-NEXT: lg %r5, 8(%r3) 135; CHECK-NEXT: lg %r4, 0(%r3) 136; CHECK-NEXT: #APP 137; CHECK-NEXT: #NO_APP 138; CHECK-NEXT: stg %r5, 8(%r2) 139; CHECK-NEXT: stg %r4, 0(%r2) 140; CHECK-NEXT: br %r14 141entry: 142 %cc_dep1 = load fp128, ptr %0, align 8 143 %1 = tail call fp128 asm sideeffect "", "={r4},0"(fp128 %cc_dep1) 144 store fp128 %1, ptr %agg.result, align 8 145 ret void 146} 147 148define float @float_and_v(float %cc_dep1) { 149; CHECK-LABEL: float_and_v: 150; CHECK: # %bb.0: # %entry 151; CHECK-NEXT: ldr %f3, %f0 152; CHECK-NEXT: #APP 153; CHECK-NEXT: #NO_APP 154; CHECK-NEXT: ldr %f0, %f3 155; CHECK-NEXT: br %r14 156entry: 157 %0 = tail call float asm sideeffect "", "={v3},0"(float %cc_dep1) 158 ret float %0 159} 160 161define double @double_and_v(double %cc_dep1) { 162; CHECK-LABEL: double_and_v: 163; CHECK: # %bb.0: # %entry 164; CHECK-NEXT: ldr %f4, %f0 165; CHECK-NEXT: #APP 166; CHECK-NEXT: #NO_APP 167; CHECK-NEXT: ldr %f0, %f4 168; CHECK-NEXT: br %r14 169entry: 170 %0 = tail call double asm sideeffect "", "={v4},0"(double %cc_dep1) 171 ret double %0 172} 173 174define void @longdouble_and_v(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) { 175; CHECK-LABEL: longdouble_and_v: 176; CHECK: # %bb.0: # %entry 177; CHECK-NEXT: vl %v5, 0(%r3), 3 178; CHECK-NEXT: #APP 179; CHECK-NEXT: #NO_APP 180; CHECK-NEXT: vst %v5, 0(%r2), 3 181; CHECK-NEXT: br %r14 182entry: 183 %cc_dep1 = load fp128, ptr %0, align 8 184 %1 = tail call fp128 asm sideeffect "", "={v5},0"(fp128 %cc_dep1) 185 store fp128 %1, ptr %agg.result, align 8 186 ret void 187} 188 189define <2 x i16> @vec32_and_r(<2 x i16> %cc_dep1) { 190; CHECK-LABEL: vec32_and_r: 191; CHECK: # %bb.0: # %entry 192; CHECK-NEXT: vlgvf %r5, %v24, 0 193; CHECK-NEXT: # kill: def $r5l killed $r5l killed $r5d 194; CHECK-NEXT: #APP 195; CHECK-NEXT: #NO_APP 196; CHECK-NEXT: vlvgf %v24, %r5, 0 197; CHECK-NEXT: br %r14 198entry: 199 %0 = tail call <2 x i16> asm sideeffect "", "={r5},0"(<2 x i16> %cc_dep1) 200 ret <2 x i16> %0 201} 202 203define <2 x i32> @vec64_and_r(<2 x i32> %cc_dep1) { 204; CHECK-LABEL: vec64_and_r: 205; CHECK: # %bb.0: # %entry 206; CHECK-NEXT: vlgvg %r4, %v24, 0 207; CHECK-NEXT: #APP 208; CHECK-NEXT: #NO_APP 209; CHECK-NEXT: vlvgg %v24, %r4, 0 210; CHECK-NEXT: br %r14 211entry: 212 %0 = tail call <2 x i32> asm sideeffect "", "={r4},0"(<2 x i32> %cc_dep1) 213 ret <2 x i32> %0 214} 215 216define <4 x i32> @vec128_and_r(<4 x i32> %cc_dep1) { 217; CHECK-LABEL: vec128_and_r: 218; CHECK: # %bb.0: # %entry 219; CHECK-NEXT: vlgvg %r3, %v24, 1 220; CHECK-NEXT: vlgvg %r2, %v24, 0 221; CHECK-NEXT: #APP 222; CHECK-NEXT: #NO_APP 223; CHECK-NEXT: vlvgp %v24, %r2, %r3 224; CHECK-NEXT: br %r14 225entry: 226 %0 = tail call <4 x i32> asm sideeffect "", "={r2},0"(<4 x i32> %cc_dep1) 227 ret <4 x i32> %0 228} 229 230define <2 x i16> @vec32_and_f(<2 x i16> %cc_dep1) { 231; CHECK-LABEL: vec32_and_f: 232; CHECK: # %bb.0: # %entry 233; CHECK-NEXT: vlr %v4, %v24 234; CHECK-NEXT: # kill: def $f4s killed $f4s killed $v4 235; CHECK-NEXT: #APP 236; CHECK-NEXT: #NO_APP 237; CHECK-NEXT: # kill: def $f4s killed $f4s def $v4 238; CHECK-NEXT: vlr %v24, %v4 239; CHECK-NEXT: br %r14 240entry: 241 %0 = tail call <2 x i16> asm sideeffect "", "={f4},0"(<2 x i16> %cc_dep1) 242 ret <2 x i16> %0 243} 244 245define <2 x i32> @vec64_and_f(<2 x i32> %cc_dep1) { 246; CHECK-LABEL: vec64_and_f: 247; CHECK: # %bb.0: # %entry 248; CHECK-NEXT: vlr %v5, %v24 249; CHECK-NEXT: # kill: def $f5d killed $f5d killed $v5 250; CHECK-NEXT: #APP 251; CHECK-NEXT: #NO_APP 252; CHECK-NEXT: # kill: def $f5d killed $f5d def $v5 253; CHECK-NEXT: vlr %v24, %v5 254; CHECK-NEXT: br %r14 255entry: 256 %0 = tail call <2 x i32> asm sideeffect "", "={f5},0"(<2 x i32> %cc_dep1) 257 ret <2 x i32> %0 258} 259 260define <4 x i32> @vec128_and_f(<4 x i32> %cc_dep1) { 261; CHECK-LABEL: vec128_and_f: 262; CHECK: # %bb.0: # %entry 263; CHECK-NEXT: vlr %v1, %v24 264; CHECK-NEXT: vrepg %v3, %v24, 1 265; CHECK-NEXT: #APP 266; CHECK-NEXT: #NO_APP 267; CHECK-NEXT: vmrhg %v24, %v1, %v3 268; CHECK-NEXT: br %r14 269entry: 270 %0 = tail call <4 x i32> asm sideeffect "", "={f1},0"(<4 x i32> %cc_dep1) 271 ret <4 x i32> %0 272} 273 274