1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=s390x-linux-gnu -mcpu=zEC12 < %s | FileCheck %s 3; 4; Test inline assembly where the operand is bitcasted. 5 6define signext i32 @int_and_f(i32 signext %cc_dep1) { 7; CHECK-LABEL: int_and_f: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: risbhg %r0, %r2, 0, 159, 32 10; CHECK-NEXT: ldgr %f1, %r0 11; CHECK-NEXT: # kill: def $f1s killed $f1s killed $f1d 12; CHECK-NEXT: #APP 13; CHECK-NEXT: #NO_APP 14; CHECK-NEXT: # kill: def $f1s killed $f1s def $f1d 15; CHECK-NEXT: lgdr %r0, %f1 16; CHECK-NEXT: risblg %r0, %r0, 0, 159, 32 17; CHECK-NEXT: lgfr %r2, %r0 18; CHECK-NEXT: br %r14 19entry: 20 %0 = tail call i32 asm sideeffect "", "={f1},0"(i32 %cc_dep1) 21 ret i32 %0 22} 23 24define i64 @long_and_f(i64 %cc_dep1) { 25; CHECK-LABEL: long_and_f: 26; CHECK: # %bb.0: # %entry 27; CHECK-NEXT: ldgr %f2, %r2 28; CHECK-NEXT: #APP 29; CHECK-NEXT: #NO_APP 30; CHECK-NEXT: lgdr %r2, %f2 31; CHECK-NEXT: br %r14 32entry: 33 %0 = tail call i64 asm sideeffect "", "={f2},0"(i64 %cc_dep1) 34 ret i64 %0 35} 36 37define void @__int128_and_f(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) { 38; CHECK-LABEL: __int128_and_f: 39; CHECK: # %bb.0: # %entry 40; CHECK-NEXT: ld %f1, 0(%r3) 41; CHECK-NEXT: ld %f3, 8(%r3) 42; CHECK-NEXT: #APP 43; CHECK-NEXT: #NO_APP 44; CHECK-NEXT: std %f1, 0(%r2) 45; CHECK-NEXT: std %f3, 8(%r2) 46; CHECK-NEXT: br %r14 47entry: 48 %cc_dep1 = load i128, ptr %0, align 8 49 %1 = tail call i128 asm sideeffect "", "={f1},0"(i128 %cc_dep1) 50 store i128 %1, ptr %agg.result, align 8 51 ret void 52} 53 54define float @float_and_r(float %cc_dep1) { 55; CHECK-LABEL: float_and_r: 56; CHECK: # %bb.0: # %entry 57; CHECK-NEXT: # kill: def $f0s killed $f0s def $f0d 58; CHECK-NEXT: lgdr %r0, %f0 59; CHECK-NEXT: risblg %r2, %r0, 0, 159, 32 60; CHECK-NEXT: #APP 61; CHECK-NEXT: #NO_APP 62; CHECK-NEXT: risbhg %r0, %r2, 0, 159, 32 63; CHECK-NEXT: ldgr %f0, %r0 64; CHECK-NEXT: # kill: def $f0s killed $f0s killed $f0d 65; CHECK-NEXT: br %r14 66entry: 67 %0 = tail call float asm sideeffect "", "={r2},0"(float %cc_dep1) 68 ret float %0 69} 70 71define double @double_and_r(double %cc_dep1) { 72; CHECK-LABEL: double_and_r: 73; CHECK: # %bb.0: # %entry 74; CHECK-NEXT: lgdr %r3, %f0 75; CHECK-NEXT: #APP 76; CHECK-NEXT: #NO_APP 77; CHECK-NEXT: ldgr %f0, %r3 78; CHECK-NEXT: br %r14 79entry: 80 %0 = tail call double asm sideeffect "", "={r3},0"(double %cc_dep1) 81 ret double %0 82} 83 84define void @longdouble_and_r(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) { 85; CHECK-LABEL: longdouble_and_r: 86; CHECK: # %bb.0: # %entry 87; CHECK-NEXT: lg %r5, 8(%r3) 88; CHECK-NEXT: lg %r4, 0(%r3) 89; CHECK-NEXT: #APP 90; CHECK-NEXT: #NO_APP 91; CHECK-NEXT: stg %r5, 8(%r2) 92; CHECK-NEXT: stg %r4, 0(%r2) 93; CHECK-NEXT: br %r14 94entry: 95 %cc_dep1 = load fp128, ptr %0, align 8 96 %1 = tail call fp128 asm sideeffect "", "={r4},0"(fp128 %cc_dep1) 97 store fp128 %1, ptr %agg.result, align 8 98 ret void 99} 100 101define <2 x i16> @vec32_and_r(<2 x i16> %cc_dep1) { 102; CHECK-LABEL: vec32_and_r: 103; CHECK: # %bb.0: # %entry 104; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d 105; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 106; CHECK-NEXT: risbgn %r3, %r2, 32, 47, 16 107; CHECK-NEXT: # kill: def $r3l killed $r3l killed $r3d 108; CHECK-NEXT: #APP 109; CHECK-NEXT: #NO_APP 110; CHECK-NEXT: srlk %r2, %r3, 16 111; CHECK-NEXT: br %r14 112entry: 113 %0 = tail call <2 x i16> asm sideeffect "", "={r3},0"(<2 x i16> %cc_dep1) 114 ret <2 x i16> %0 115} 116 117define <2 x i32> @vec64_and_r(<2 x i32> %cc_dep1) { 118; CHECK-LABEL: vec64_and_r: 119; CHECK: # %bb.0: # %entry 120; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 121; CHECK-NEXT: sllg %r5, %r2, 32 122; CHECK-NEXT: lr %r5, %r3 123; CHECK-NEXT: #APP 124; CHECK-NEXT: #NO_APP 125; CHECK-NEXT: lgr %r3, %r5 126; CHECK-NEXT: srlg %r2, %r5, 32 127; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 128; CHECK-NEXT: # kill: def $r3l killed $r3l killed $r3d 129; CHECK-NEXT: br %r14 130entry: 131 %0 = tail call <2 x i32> asm sideeffect "", "={r5},0"(<2 x i32> %cc_dep1) 132 ret <2 x i32> %0 133} 134 135define <2 x i16> @vec32_and_f(<2 x i16> %cc_dep1) { 136; CHECK-LABEL: vec32_and_f: 137; CHECK: # %bb.0: # %entry 138; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d 139; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 140; CHECK-NEXT: risbgn %r3, %r2, 32, 47, 16 141; CHECK-NEXT: risbhg %r0, %r3, 0, 159, 32 142; CHECK-NEXT: ldgr %f3, %r0 143; CHECK-NEXT: # kill: def $f3s killed $f3s killed $f3d 144; CHECK-NEXT: #APP 145; CHECK-NEXT: #NO_APP 146; CHECK-NEXT: # kill: def $f3s killed $f3s def $f3d 147; CHECK-NEXT: lgdr %r0, %f3 148; CHECK-NEXT: risblg %r3, %r0, 0, 159, 32 149; CHECK-NEXT: srlk %r2, %r3, 16 150; CHECK-NEXT: br %r14 151entry: 152 %0 = tail call <2 x i16> asm sideeffect "", "={f3},0"(<2 x i16> %cc_dep1) 153 ret <2 x i16> %0 154} 155 156define <2 x i32> @vec64_and_f(<2 x i32> %cc_dep1) { 157; CHECK-LABEL: vec64_and_f: 158; CHECK: # %bb.0: # %entry 159; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 160; CHECK-NEXT: sllg %r0, %r2, 32 161; CHECK-NEXT: lr %r0, %r3 162; CHECK-NEXT: ldgr %f4, %r0 163; CHECK-NEXT: #APP 164; CHECK-NEXT: #NO_APP 165; CHECK-NEXT: lgdr %r3, %f4 166; CHECK-NEXT: srlg %r2, %r3, 32 167; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 168; CHECK-NEXT: # kill: def $r3l killed $r3l killed $r3d 169; CHECK-NEXT: br %r14 170entry: 171 %0 = tail call <2 x i32> asm sideeffect "", "={f4},0"(<2 x i32> %cc_dep1) 172 ret <2 x i32> %0 173} 174 175define <4 x i32> @vec128_and_f(<4 x i32> %cc_dep1) { 176; CHECK-LABEL: vec128_and_f: 177; CHECK: # %bb.0: # %entry 178; CHECK-NEXT: aghi %r15, -176 179; CHECK-NEXT: .cfi_def_cfa_offset 336 180; CHECK-NEXT: # kill: def $r4l killed $r4l def $r4d 181; CHECK-NEXT: sllg %r0, %r4, 32 182; CHECK-NEXT: lr %r0, %r5 183; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 184; CHECK-NEXT: stg %r0, 168(%r15) 185; CHECK-NEXT: sllg %r0, %r2, 32 186; CHECK-NEXT: lr %r0, %r3 187; CHECK-NEXT: stg %r0, 160(%r15) 188; CHECK-NEXT: ld %f0, 160(%r15) 189; CHECK-NEXT: ld %f2, 168(%r15) 190; CHECK-NEXT: #APP 191; CHECK-NEXT: #NO_APP 192; CHECK-NEXT: lgdr %r3, %f0 193; CHECK-NEXT: lgdr %r5, %f2 194; CHECK-NEXT: srlg %r2, %r3, 32 195; CHECK-NEXT: srlg %r4, %r5, 32 196; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 197; CHECK-NEXT: # kill: def $r3l killed $r3l killed $r3d 198; CHECK-NEXT: # kill: def $r4l killed $r4l killed $r4d 199; CHECK-NEXT: # kill: def $r5l killed $r5l killed $r5d 200; CHECK-NEXT: aghi %r15, 176 201; CHECK-NEXT: br %r14 202entry: 203 %0 = tail call <4 x i32> asm sideeffect "", "={f0},0"(<4 x i32> %cc_dep1) 204 ret <4 x i32> %0 205} 206 207