1; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs | FileCheck %s 2; 3; Test that a def operand of super-reg is not dropped during post RA pseudo 4; expansion in expandZExtPseudo(). 5 6define void @fun_llvm_stress_reduced(ptr, ptr, ptr, i32) { 7; CHECK: .text 8BB: 9 %A = alloca i32 10 %Sl24 = select i1 undef, ptr %1, ptr %1 11 %L26 = load i16, ptr undef 12 %L32 = load i32, ptr %Sl24 13 br label %CF847 14 15CF847: ; preds = %CF878, %BB 16 %L61 = load i16, ptr undef 17 br label %CF878 18 19CF878: ; preds = %CF847 20 %Sl67 = select i1 undef, <2 x i32> undef, <2 x i32> undef 21 %Cmp68 = icmp ugt i32 undef, %3 22 br i1 %Cmp68, label %CF847, label %CF863 23 24CF863: ; preds = %CF878 25 %L84 = load i16, ptr undef 26 br label %CF825 27 28CF825: ; preds = %CF825, %CF863 29 %Sl105 = select i1 undef, i1 undef, i1 undef 30 br i1 %Sl105, label %CF825, label %CF856 31 32CF856: ; preds = %CF856, %CF825 33 %Cmp114 = icmp ult i16 -24837, %L61 34 br i1 %Cmp114, label %CF856, label %CF875 35 36CF875: ; preds = %CF856 37 %Shuff124 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> <i32 1, i32 3> 38 br label %CF827 39 40CF827: ; preds = %CF923, %CF911, %CF875 41 %Sl142 = select i1 undef, i64 undef, i64 -1 42 %B148 = sdiv i32 409071, 409071 43 %E153 = extractelement <2 x i32> %Shuff124, i32 1 44 br label %CF911 45 46CF911: ; preds = %CF827 47 br i1 undef, label %CF827, label %CF867 48 49CF867: ; preds = %CF911 50 br label %CF870 51 52CF870: ; preds = %CF870, %CF867 53 store i8 0, ptr %0 54 %FC176 = fptoui double undef to i1 55 br i1 %FC176, label %CF870, label %CF923 56 57CF923: ; preds = %CF870 58 %L179 = load i16, ptr undef 59 %Sl191 = select i1 undef, ptr %A, ptr %A 60 br i1 false, label %CF827, label %CF828 61 62CF828: ; preds = %CF905, %CF923 63 %B205 = urem i16 -7553, undef 64 %E209 = extractelement <2 x i32> %Sl67, i32 1 65 %Cmp215 = icmp ugt i16 %L179, 0 66 br label %CF905 67 68CF905: ; preds = %CF828 69 %E231 = extractelement <4 x i1> undef, i32 1 70 br i1 %E231, label %CF828, label %CF829 71 72CF829: ; preds = %CF909, %CF829, %CF905 73 %B234 = udiv i16 %L26, %L84 74 br i1 undef, label %CF829, label %CF894 75 76CF894: ; preds = %CF894, %CF829 77 store i64 %Sl142, ptr %Sl191 78 %Sl241 = select i1 %Cmp114, i1 false, i1 %Cmp215 79 br i1 %Sl241, label %CF894, label %CF907 80 81CF907: ; preds = %CF894 82 %B247 = udiv i32 0, %E153 83 br label %CF909 84 85CF909: ; preds = %CF907 86 store i1 %FC176, ptr undef 87 %Cmp263 = icmp ugt i1 undef, %Sl241 88 br i1 %Cmp263, label %CF829, label %CF830 89 90CF830: ; preds = %CF909 91 %B304 = urem i16 %L84, %B205 92 %I311 = insertelement <2 x i32> %Shuff124, i32 %B247, i32 1 93 store i8 0, ptr %0 94 %Sl373 = select i1 %Cmp68, i32 0, i32 %E153 95 br label %CF833 96 97CF833: ; preds = %CF880, %CF830 98 br label %CF880 99 100CF880: ; preds = %CF833 101 %Cmp412 = icmp ne i16 %B234, -18725 102 br i1 %Cmp412, label %CF833, label %CF865 103 104CF865: ; preds = %CF880 105 store double 0.000000e+00, ptr %Sl24 106 br label %CF860 107 108CF860: ; preds = %CF860, %CF865 109 store i8 0, ptr %2 110 %Cmp600 = icmp sge i32 %B148, undef 111 br i1 %Cmp600, label %CF860, label %CF913 112 113CF913: ; preds = %CF860 114 store i32 %E209, ptr undef 115 store i32 %Sl373, ptr undef 116 %Cmp771 = icmp ule i32 undef, %L32 117 br label %CF842 118 119CF842: ; preds = %CF925, %CF913 120 br label %CF925 121 122CF925: ; preds = %CF842 123 %Cmp778 = icmp sgt i1 %Cmp771, %Sl241 124 br i1 %Cmp778, label %CF842, label %CF898 125 126CF898: ; preds = %CF925 127 %Sl785 = select i1 %Cmp600, i16 undef, i16 %B304 128 unreachable 129} 130