xref: /llvm-project/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints-02.mir (revision 16b7cc69ef43110c9776212379ccc37d7d3263c0)
1# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 -start-before=greedy %s -o - \
2# RUN:   | FileCheck %s
3#
4# Test that two-address reg alloc hints are given so that a SELR becomes LOCR.
5
6
7--- |
8  define i32 @fun(i32 %arg, i32 %arg1, i32 %arg2, ptr %arg3) { ret i32 0 }
9  declare void @foo(i32)
10...
11# CHECK-LABEL: fun
12# CHECK: locr
13
14---
15name:            fun
16alignment:       16
17tracksRegLiveness: true
18registers:
19  - { id: 0, class: gr32bit }
20  - { id: 1, class: gr32bit }
21  - { id: 2, class: gr32bit }
22  - { id: 3, class: gr32bit }
23  - { id: 4, class: gr64bit }
24  - { id: 5, class: grx32bit }
25  - { id: 6, class: grx32bit }
26  - { id: 7, class: addr64bit }
27  - { id: 8, class: grx32bit }
28  - { id: 9, class: grx32bit }
29  - { id: 10, class: gr64bit }
30  - { id: 11, class: gr32bit }
31frameInfo:
32  maxAlignment:    1
33  adjustsStack:    true
34  hasCalls:        true
35machineFunctionInfo: {}
36body:             |
37  bb.0:
38    %5:grx32bit = LHIMux 88
39    %8:grx32bit = LHIMux 77
40    %9:grx32bit = LHIMux 66
41
42  bb.1:
43    %6:grx32bit = LLCMux undef %7:addr64bit, 0, $noreg :: (load (s8) from `ptr undef`)
44    CHIMux %6, 1, implicit-def $cc
45    %11:gr32bit = SELRMux %8, %9:grx32bit, 14, 6, implicit killed $cc
46    CHIMux %6, 2, implicit-def $cc
47    %0:gr32bit = SELRMux %11, %5, 14, 8, implicit killed $cc
48    %10:gr64bit = LGFR %0
49    $r2d = COPY %10
50    CallBRASL @foo, killed $r2d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit $fpc
51    J %bb.1
52
53...
54